CY7C1370C-200AI Cypress Semiconductor Corporation., CY7C1370C-200AI Datasheet

CY7C1370C-200AI

Manufacturer Part Number

CY7C1370C-200AI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1370C-200AI.pdf (27 pages)

2.CY7C1370C-200AI.pdf (27 pages)

3.CY7C1370C-200AI.pdf (27 pages)

Specifications of CY7C1370C-200AI

Case

TQFP100

Date_code

Current page: 1 of 27
Download datasheet (535Kb)

Cypress Semiconductor Corporation

Document #: 38-05233 Rev. *D

Features

Logic Block Diagram-CY7C1370C (512K x 36)

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

• Internally self-timed output buffer control to eliminate

• Fully registered (inputs and outputs) for pipelined

• Byte Write capability

• Single 3.3V power supply

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

— Available speed grades are 250, 225, 200 and

the need to use asynchronous OE

operation

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

packages

167 MHz

CEN

CLK

A0, A1, A

ADV/LD

MODE

CE1

CE2

CE3

WRITE ADDRESS

ADDRESS

CONTROL

READ LOGIC

SLEEP

AND DATA COHERENCY

•

WRITE REGISTRY

CONTROL LOGIC

WRITE ADDRESS

ADV/LD

3901 North First Street

512K x 36/1M x 18 Pipelined SRAM

BURST

LOGIC

A0'

A1'

DRIVERS

Functional Description

The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and

1M x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL¥ logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1370C and CY7C1372C are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1370C and CY7C1372C are

pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

and a Write Enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

WRITE

–BW

MEMORY

ARRAY

INPUT

•

with NoBL™ Architecture

for CY7C1370C and BW

San Jose

INPUT

CA 95134

Revised June 03, 2004

–BW

DQs

DQP

, CE

•

CY7C1370C

CY7C1372C

for CY7C1372C)

408-943-2600

, CE

) and an

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