CY7C1360B-200AI Cypress Semiconductor Corporation., CY7C1360B-200AI Datasheet

CY7C1360B-200AI

Manufacturer Part Number

CY7C1360B-200AI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1360B-200AI.pdf (34 pages)

2.CY7C1360B-200AI.pdf (34 pages)

3.CY7C1360B-200AI.pdf (34 pages)

Specifications of CY7C1360B-200AI

Case

TQFP

Date_code

04+

Current page: 1 of 34
Download datasheet (647Kb)

Cypress Semiconductor Corporation

Document #: 38-05291 Rev. *C

Features

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

• Supports bus operation up to 225 MHz

• Available speed grades are 225, 200 and 166 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

Pentium

and 165-Ball fBGA packages

is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

interleaved or linear burst sequences

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

•

3901 North First Street

225 MHz

250

2.8

Functional Description

The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36

and 524,288 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable ( CE

Enables (CE

and ADV ), Write Enables ( BW

( GW ). Asynchronous inputs include the Output Enable ( OE )

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor ( ADSP ) or

Address Strobe Controller ( ADSC ) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin ( ADV ).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1360B/CY7C1362B operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

•

200 MHz

220

and CE

3.0

San Jose

[2]

), Burst Control inputs ( ADSC , ADSP ,

CA 95134

[1]

166 MHz

, and BWE ), and Global Write

180

3.5

), depth-expansion Chip

Revised April 9, 2004

•

CY7C1360B

CY7C1362B

408-943-2600

Unit

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