74ALVCH16843DGG,11 NXP Semiconductors, 74ALVCH16843DGG,11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16843DGG,11
• Description: IC 18BIT BUS INTRFC D 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16843DGG,11

• Logic Type: D-Type Transparent Latch
• Circuit: 9:9
• Output Type: Tri-State
• Voltage - Supply: 2.3 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 2.2ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16843DG-T; 74ALVCH16843DG-T; 935259110118

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
1998 Aug 04
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
MULTIBYTE
Low inductance multiple V
and ground bounce
All data inputs have bus hold
Output drive capability 50 transmission lines @ 85 C
18-bit bus interface D-type latch (3-State)
t
t
C
C
C
PHL
PHL
P
f
SYMBOL
o
I
PD
PD
PD
D
= output frequency in MHz; V
= C
/t
/t
PLH
PLH
is used to determine the dynamic power dissipation (P
PD
amb
TM
V
= 25 C; t
CC
24 mA at 3.0 V
flow-through standard pin-out architecture
Propagation delay
nDn to nQn
Propagation delay
nLE to nQn
Input capacitance
Power dissipation capacitance per buffer
Power dissi ation ca acitance er buffer
2
f
i
PACKAGES
+ S (C
r
= t
CC
f
L
and GND pins for minimum noise
2.5ns
PARAMETER
V
CC
CC
= supply voltage in V; S (C
2
f
o
) where: f
i
= input frequency in MHz; C
D
TEMPERATURE
–40 C to +85 C
in W):
L
V
V
V
V
V
V
CC
CC
CC
CC
I
I
RANGE
= GND to V
= GND to V
V
CC
= 2.5V, C
= 3.3V, C
= 2.5V, C
= 3.3V, C
2
2
PIN CONFIGURATION
f
o
) = sum of outputs.
L
L
L
L
CC
CC
= 30pF
= 50pF
= 30pF
= 50pF
1
1
L
CONDITIONS
74ALVCH16843 DGG
= output load capacitance in pF;
OUTSIDE NORTH
AMERICA
1CLR
2CLR
GND
GND
GND
GND
1OE
2OE
V
V
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
CC
CC
transparent mode
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output disabled
Output disabled
Output enabled
Output enabled
Clocked mode
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
1
2
3
4
5
6
7
8
9
NORTH AMERICA
ACH16843 DGG
74ALVCH16843
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TYPICAL
SH00143
1LE
1D
GND
1D
1D
V
1D
1D
1D
GND
1D
1D
1D
2D
2D
2D
GND
2D
2D
2D
V
2D
2D
GND
2D
Product specification
1PRE
2PRE
CC
CC
2.2
2.1
2.3
2.0
5.0
17
19
2LE
3
9
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
853–2108 019833
DRAWING
SOT364-1
NUMBER
UNIT
pF
pF
ns
ns
F