74LVC162373ADGG,11 NXP Semiconductors, 74LVC162373ADGG,11 Datasheet - Page 2

• Manufacturer Part Number: 74LVC162373ADGG,11
• Description: IC 16BIT D TRANSP LATCH 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC162373ADGG,11

• Logic Type: D-Type Transparent Latch
• Package / Case: 48-TSSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 1.2 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 3.3ns
• Current - Output High, Low: 12mA, 12mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LVC
• Polarity: Non-Inverting
• Input Bias Current (max): 0.1 uA
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Propagation Delay Time: 12 ns at 1.2 V, 3.3 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935237720118

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2004 Feb 05
t
t
t
C
C
PHL
PZH
PHZ
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bushold (74LVCH162373A only)
High-impedance when V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
16-bit D-type transparent latch; 30
resistors; 5 V tolerant inputs/outputs; 3-state
SYMBOL
P
f
f
C
i
o
/t
/t
/t
D
PD
= input frequency in MHz;
L
PLH
PZL
PLZ
= output frequency in MHz;
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
PD
amb
V
CC
= 25 C; t
propagation delay nDn to nQn
propagation delay nLE to nQn
3-state output enable time nOE to nQn C
3-state output disable time nOE to nQn C
input capacitance
power dissipation per latch
2
f
i
N + (C
CC
r
= t
= 0 V
PARAMETER
f
2.5 ns
L
V
CC
2
f
o
) where:
C
C
V
2
CC
L
L
L
L
outputs enabled
outputs disabled
series termination
DESCRIPTION
The 74LVC(H)162373A is a 16-bit D-type transparent
latch featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. One latch
enable (pin nLE) input and one output enable (pin nOE)
are provided for each octal. Inputs can be driven from
either 3.3 or 5 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices
in a mixed 3.3 and 5 V environment.
The 74LVC(H)162373A consists of 2 sections of eight
D-type transparent latches with 3-state true outputs. When
pin nLE is HIGH, data at the corresponding data inputs
(pins nDn) enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time
its corresponding data inputs changes.
When pin nLE is LOW the latches store the information
that was present at the data inputs a set-up time preceding
the HIGH-to-LOW transition of pin nLE. When pin nOE is
LOW, the contents of the eight latches are available at the
outputs. When pin nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
The 74LVCH162373A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
The 74LVC(H)162373A is designed with 30
termination resistors in both high and low output stages to
reduce line noise.
= 50 pF; V
= 50 pF; V
= 50 pF; V
= 50 pF; V
D
= 3.3 V; notes 1 and 2
in W).
CONDITIONS
CC
CC
CC
CC
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
3.3
3.5
4.0
3.4
5.0
26
19
TYPICAL
74LVCH162373A
74LVC162373A;
Product specification
ns
ns
ns
ns
pF
pF
pF
series
UNIT