74LV259BQ,115 NXP Semiconductors, 74LV259BQ,115 Datasheet - Page 4

• Manufacturer Part Number: 74LV259BQ,115
• Description: IC 8BIT ADDRESS LATCH 16-DHVQFN
• Manufacturer: NXP Semiconductors
• Series: 74LVr

Specifications of 74LV259BQ,115

• Logic Type: D-Type, Addressable
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Circuit: 1:8
• Output Type: Standard
• Voltage - Supply: 1 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 36ns
• Current - Output High, Low: 6mA, 6mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: LV
• Polarity: Non-Inverting
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Propagation Delay Time: 105 ns at 1.2 V, 36 ns at 2 V, 26 ns at 2.7 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LV259BQ-G; 74LV259BQ-G; 935285578115

NXP Semiconductors
Table 2.
6. Functional description
Table 3.
H = HIGH voltage level; L = LOW voltage level
Table 4.
H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = High or LOW data one set-up time prior to the
LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared
74LV259_3
Product data sheet
Symbol
D
LE
MR
V
LE
L
H
L
H
Operating modes
master reset
demultiplex (active
HIGH) decoder
(when D = H)
store (do nothing)
addressable latch
CC
Pin description
Mode select table
Function table
Pin
13
14
15
16
Input
MR
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
…continued
LE
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
H
A0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
MR
H
H
L
L
A1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
Rev. 03 — 2 January 2008
A2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
Description
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
Output
Q0
L
Q = d
L
L
L
L
L
L
L
q0
Q = d
q0
q0
q0
q0
q0
q0
q0
Q1
L
L
Q = d
L
L
L
L
L
L
q1
q1
Q = d
q1
q1
q1
q1
q1
q1
Q2
L
L
L
Q = d
L
L
L
L
L
q2
q2
q2
Q = d
q2
q2
q2
q2
q2
Mode
addressable latch
memory
active HIGH 8-channel demultiplexer
reset
Q3
L
L
L
L
Q = d
L
L
L
L
q3
q3
q3
q3
Q = d
q3
q3
q3
q3
Q4
L
L
L
L
L
Q = d
L
L
L
q4
q4
q4
q4
q4
Q = d
q4
q4
q4
8-bit addressable latch
Q5
L
L
L
L
L
L
Q = d
L
L
q5
q5
q5
q5
q5
q5
Q = d q6
q5
q5
© NXP B.V. 2008. All rights reserved.
74LV259
Q6
L
L
L
L
L
L
Q = d L
L
q6
q6
q6
q6
q6
q6
Q = d q7
q6
Q7
L
L
L
L
L
L
L
Q = d
q7
q7
q7
q7
q7
q7
q7
Q = d
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