74AHC573PW,118 NXP Semiconductors, 74AHC573PW,118 Datasheet - Page 5

• Manufacturer Part Number: 74AHC573PW,118
• Description: IC OCTAL D TRANSP LATCH 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AHCr

Specifications of 74AHC573PW,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-TSSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 3.9ns
• Current - Output High, Low: 8mA, 8mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 8
• Logic Family: AHC
• Polarity: Non-Inverting
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Propagation Delay Time: 4.2 ns at 5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AHC573PW-T; 74AHC573PW-T; 935263072118

NXP Semiconductors
6. Functional description
Table 3.
[1]
7. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1]
[2]
74AHC_AHCT573
Product data sheet
Operating mode
Enable and read register (transparent
mode)
Latch and read register
Latch register and disable outputs
Symbol
V
V
I
I
I
I
I
T
P
IK
OK
O
CC
GND
stg
CC
I
tot
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70 C the value of P
For TSSOP20 packages: above 60 C the value of P
For DHVQFN20 packages: above 60 C the value of P
Function table
Limiting values
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
[1]
All information provided in this document is subject to legal disclaimers.
Input
OE
L
L
H
tot
Rev. 6 — 25 November 2010
Conditions
V
V
V
T
derates linearly at 8 mW/K.
amb
I
O
O
tot
< 0.5 V
< 0.5 V or V
= 0.5 V to (V
tot
derates linearly at 5.5 mW/K.
= 40 C to +125 C
derates linearly with 4.5 mW/K.
LE
H
L
L
O
CC
> V
74AHC573; 74AHCT573
+ 0.5 V)
CC
+ 0.5 V
Dn
L
H
l
h
l
h
Octal D-type transparant latch; 3-state
Internal latch
L
H
L
H
L
H
[1]
[1]
[2]
Min
0.5
0.5
20
20
25
-
75
65
-
© NXP B.V. 2010. All rights reserved.
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
L
Output
Qn
L
H
H
Z
Z
Unit
V
V
mA
mA
mA
mA
mA
C
mW
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