ISPPACCLK5520V01TN100I Lattice Semiconductor Corp., ISPPACCLK5520V01TN100I Datasheet

ISPPACCLK5520V01TN100I

Manufacturer Part Number

ISPPACCLK5520V01TN100I

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPPACCLK5510V-01TN48C.pdf (48 pages)

Specifications of ISPPACCLK5520V01TN100I

Lead_time

2 weeks

Current page: 1 of 48
Download datasheet (540Kb)

March 2005

Features

■ 10MHz to 320MHz Input/Output Operation

■ Low Output to Output Skew (<50ps)

■ Low Jitter Peak-to-Peak(<70ps)

■ Up to 20 Programmable Fan-out Buffers

■ Fully Integrated High-Performance PLL

■ Precision Programmable Phase Adjustment

Product Family Block Diagram

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

(Skew) Per Output

• Programmable output standards and individual

• Programmable output impedance

• Programmable slew rate

• Up to 10 banks with individual V

• Programmable lock detect

• Multiply and divide ratio controlled by

• Programmable On-chip Loop Filter

• 16 settings; minimum step size 195ps

• Up to +/- 12ns skew range

• Coarse and ﬁne adjustment modes

enable controls

- LVTTL, LVCMOS, HSTL, SSTL, LVDS,

- 40 to 70 Ω in 5 Ω increments

- 1.5V, 1.8V, 2.5V, 3.3V

- Input divider (5 bits)

- Internal feedback divider (5 bits)

- Five output dividers (5 bits)

- Locked to VCO frequency

* Input Available only on ispClock 5520

LVPECL

LOCK DETECT

FREQUENCY

DETECTOR

PHASE/

INTERFACE

MEMORY

JTAG

PLL CORE

CMOS

FILTER

CCO

and GND

INTERNAL FEEDBACK PATH

Management Logic

VCO

Multiple Profile

BYPASS

■ Up to Five Clock Frequency Domains

■ Flexible Clock Reference Inputs

■ Four User-programmable Proﬁles Stored in

■ Full JTAG Boundary Scan Test In-System

■ Exceptional Power Supply Noise Immunity

■ Commercial (0 to 70°C) and Industrial

■ 100-pin and 48-pin TQFP Packages

■ Applications

ispClock 5500 Family

MUX

In-System Programmable Clock Generator

Programming Support

(-40 to 85°C) Temperature Ranges

• Programmable input standards

• Clock A/B selection multiplexer

• Programmable precision termination

• Supports both test and multiple operating

• Circuit board common clock generation and

• PLL-based frequency generation

• High fan-out clock buffer

CMOS

conﬁgurations

distribution

- LVTTL, LVCMOS, SSTL, HSTL, LVDS,

DIVIDERS

OUTPUT

LVPECL

Memory

with Universal Fan-Out Buffer

ROUTING

OUTPUT

MATRIX

™

CONTROL

SKEW

DRIVERS

OUTPUT

clk5500_06.2

Data Sheet

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