CYD18S72V-100BBXI Cypress Semiconductor Corporation., CYD18S72V-100BBXI Datasheet

CYD18S72V-100BBXI

Manufacturer Part Number

CYD18S72V-100BBXI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CYD18S72V-100BBXC.pdf (25 pages)

2.CYD18S72V-100BBXC.pdf (25 pages)

Specifications of CYD18S72V-100BBXI

Package

BGA

Date_code

10+

Current page: 1 of 25
Download datasheet (701Kb)

Cypress Semiconductor Corporation

Document #: 38-06069 Rev. *I

Features

Table 1. Product Selection Guide

Part Number

Max. Speed (MHz)

Max. Access Time—Clock to Data (ns)

Typical operating current (mA)

Package

• True dual-ported memory cells that allow simultaneous

• Synchronous pipelined operation

• Family of 4-Mbit, 9-Mbit, and 18-Mbit devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

• 3.3V low power

• Mailbox function for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 484-ball FBGA (1-mm pitch)

• Pb-Free packaging available

• Counter wrap around control

• Counter readback on address lines

• Mask register readback on address lines

• Dual Chip Enables on both ports for easy depth

• Seamless Migration to Next Generation Dual-Port

access of the same memory location

— Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

expansion

Family

Density

•

198 Champion Court

FLEx72™ 3.3V 64K/128K/256K x 72

23 mm x 23 mm

484-ball FBGA

CYD04S72V

(64K x 72)

4-Mbit

167

225

4.0

Functional Description

The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit

pipelined, synchronous, true dual-port static RAMs that are

high-speed, low-power 3.3V CMOS. Two ports are provided,

permitting independent, simultaneous access to any location

in memory. The result of writing to the same location by more

than one port at the same time is undefined. Registers on

control, address, and data lines allow for minimal set-up and

hold time.

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal write pulse width is

independent of the duration of the R/W input signal. The

internal write pulse is self-timed to allow the shortest possible

cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

The CYD18S72V device have limited features. Please see

“Address Counter and Mask Register Operations

page 6“ for details.

Seamless Migration to Next-Generation Dual-Port Family

Cypress offers a migration path for all devices to the

next-generation devices in the Dual-Port family with a

compatible footprint. Please contact Cypress Sales for more

details.

Synchronous Dual-Port RAM

•

San Jose

23 mm x 23 mm

484-ball FBGA

CYD09S72V

(128K x 72)

9-Mbit

167

270

4.0

CA 95134-1709

Revised May 2, 2006

CYD04S72V

CYD09S72V

CYD18S72V

23 mm x 23 mm

484-ball FBGA

CYD18S72V

•

(256K x 72)

18-Mbit

133

410

5.0

408-943-2600

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