CY7C1470V25-200AXI Cypress Semiconductor Corporation., CY7C1470V25-200AXI Datasheet

CY7C1470V25-200AXI

Manufacturer Part Number

CY7C1470V25-200AXI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1474V25.pdf (28 pages)

2.CY7C1470V25-200AXI.pdf (28 pages)

Specifications of CY7C1470V25-200AXI

Package

QFP

Date_code

09+

Current page: 1 of 28
Download datasheet (510Kb)

Cypress Semiconductor Corporation

Document #: 38-05290 Rev. *I

Features

Logic Block Diagram-CY7C1470V25 (2M x 36)

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

• Internally self-timed output buffer control to eliminate

• Fully registered (inputs and outputs) for pipelined

• Byte Write capability

• Single 2.5V power supply

• 2.5V/1.8V I/O supply (V

• Fast clock-to-output times

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• CY7C1470V25, CY7C1472V25 available in

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

— Available speed grades are 250, 200 and 167 MHz

the need to use asynchronous OE

operation

— 3.0 ns (for 250-MHz device)

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1474V25

available in lead-free and non-lead-free 209 ball FBGA

package

CEN

CLK

A0, A1, A

ADV/LD

MODE

CE1

CE2

CE3

DDQ

)

WRITE ADDRESS

ADDRESS

Pipelined SRAM with NoBL™ Architecture

CONTROL

READ LOGIC

•

SLEEP

AND DATA COHERENCY

WRITE REGISTRY

CONTROL LOGIC

198 Champion Court

WRITE ADDRESS

ADV/LD

72-Mbit(2M x 36/4M x 18/1M x 72)

BURST

LOGIC

A0'

A1'

Functional Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,

2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs

with No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations

CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped

with the advanced (NoBL) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of data in systems that require frequent Write/Read

transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25

are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle. Write operations are controlled by the

Byte Write Selects (BW

for CY7C1470V25 and BW

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

DRIVERS

WRITE

•

MEMORY

San Jose

ARRAY

INPUT

with

CA 95134-1709

–BW

INPUT

–BW

for CY7C1474V25, BW

Revised June 21, 2006

wait

for CY7C1472V25) and a

CY7C1470V25

CY7C1472V25

CY7C1474V25

, CE

•

DQs

DQP

states.

, CE

408-943-2600

) and an

–BW

The

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