74AUP1G57GF,132 NXP Semiconductors, 74AUP1G57GF,132 Datasheet - Page 4

• Manufacturer Part Number: 74AUP1G57GF,132
• Description: IC CONFIG MULTI-FUNC GATE 6-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1G57GF,132

• Number Of Circuits: 1
• Package / Case: 6-XSON, SOT891
• Logic Type: Configurable Multiple Function
• Number Of Inputs: 3
• Schmitt Trigger Input: Yes
• Output Type: Single-Ended
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: MUX Gates
• Logic Family: 74AUP
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Propagation Delay Time: 20.9 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 20 mA
• Output Voltage: 4.6 V
• Power Dissipation: 250 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP1G57GF-H 935281328132

NXP Semiconductors
Table 5.
74AUP1G57
Product data sheet
Logic function
2-input AND
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
Fig 5.
Fig 7.
Fig 9.
2-input AND gate or 2-input NOR gate with
both inputs inverted
2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
2-input XNOR gate
C
C
C
C
C
B
B
A
A
B
Function selection table
7.1 Logic configurations
Y
Y
Y
Y
Y
B
B
A
1
2
3
1
2
3
1
2
3
6
5
4
001aab584
6
5
4
001aab586
6
5
4
001aab588
All information provided in this document is subject to legal disclaimers.
C
Y
C
Y
C
Y
V
V
V
CC
CC
CC
Rev. 4 — 20 July 2010
Figure
see
see
see
see
see
see
see
see
see
Fig 6.
Fig 8.
Fig 10. Inverter
Figure 5
Figure 8
Figure 6
Figure 6
Figure 8
Figure 5
Figure 9
Figure 10
Figure 11
Low-power configurable multiple function gate
2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
2-input NOR gate or 2-input AND gate with
both inputs inverted
C
C
C
C
B
B
A
A
A
and
and
Figure 7
Figure 7
Y
Y
Y
Y
Y
A
B
A
74AUP1G57
1
2
3
1
2
3
1
2
3
6
5
4
001aab589
© NXP B.V. 2010. All rights reserved.
6
5
4
6
5
4
001aab585
001aab587
Y
C
Y
C
Y
V
V
V
CC
CC
CC
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