ISPLSI3256A90LQ Lattice Semiconductor Corp., ISPLSI3256A90LQ Datasheet

ISPLSI3256A90LQ

Manufacturer Part Number

ISPLSI3256A90LQ

Description

QFP-160

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI3256A70LQI.pdf (13 pages)

Specifications of ISPLSI3256A90LQ

Date_code

10+

Current page: 1 of 13
Download datasheet (164Kb)

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH-PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

3256a_09

Features

— 128 I/O Pins

— 11000 PLD Gates

— 384 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— 5V In-System Programmable (ISP™) using Lattice

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Market, and Improved Product Quality

ISP or Boundary Scan Test (IEEE 1149.1) Protocol

Machines, Address Decoders, etc.

Logic and Structured Designs

mize Switching Noise

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 90 MHz Maximum Operating Frequency

pd = 12 ns Propagation Delay

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 3256A is a High-Density Programmable Logic

Device containing 384 Registers, 128 Universal I/O pins,

five Dedicated Clock Input Pins, eight Output Routing

Pools (ORP) and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3256A features 5V in-system

programmability and in-system diagnostic capabilities.

The ispLSI 3256A offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3256A device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.

There are a total of 32 Twin GLBs in the ispLSI 3256A

device. Each Twin GLB has 24 inputs, a programmable

AND array and two OR/Exclusive-OR Arrays, and eight

outputs which can be configured to be either combinato-

rial or registered. All Twin GLB inputs come from the

GRP.

Functional Block Diagram

Description

Output Routing Pool

ispLSI

Global Routing Pool

Array

Output Routing Pool

D Q

Output Routing Pool

Twin

GLB

3256A

May 1999

Boundary

Scan

0139A

Related parts for ISPLSI3256A90LQ

Related keywords

ISPLSI3256A90LQ datasheet
ISPLSI3256A90LQ data sheet
ISPLSI3256A90LQ pdf datasheet
ISPLSI3256A90LQ component
ISPLSI3256A90LQ part
ISPLSI3256A90LQ distributor
ISPLSI3256A90LQ RoHS
ISPLSI3256A90LQ datasheet download