ISPLSI1024EA100LT100 Lattice Semiconductor Corp., ISPLSI1024EA100LT100 Datasheet

ISPLSI1024EA100LT100

Manufacturer Part Number

ISPLSI1024EA100LT100

Description

QFP100

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI1024EA100LT100.pdf (13 pages)

Specifications of ISPLSI1024EA100LT100

Date_code

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• HIGH DENSITY PROGRAMMABLE LOGIC

• NEW FEATURES

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

1024ea_02

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Features

— 4000 PLD Gates

— 48 I/O Pins, Two Dedicated Inputs

— 144 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable via IEEE 1149.1

— User Selectable 3.3V or 5V I/O Supports Mixed-

— Open-Drain Output Option

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

Machines, Address Decoders, etc.

(JTAG) Test Access Port

Voltage Systems (V

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 200 MHz Maximum Operating Frequency

pd = 4.5 ns Propagation Delay

CCIO

CMOS

Pin)

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 1024EA is a High Density Programmable

Logic Device containing 144 Registers, 48 Universal I/O

pins, two Dedicated Input pins, four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1024EA features 5V in-system

diagnostic capabilities via IEEE 1149.1 Test Access Port.

The ispLSI 1024EA device offers non-volatile

reprogrammability of the logic, as well as the intercon-

nects to provide truly reconfigurable systems. A functional

superset of the ispLSI 1024 architecture, the ispLSI

1024EA device adds user selectable 3.3V or 5V I/O and

open-drain output options.

The basic unit of logic on the ispLSI 1024EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…D7 (Figure 1). There are a total of 24 GLBs in the

ispLSI 1024EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and dedicated inputs. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

Functional Block Diagram

Description

ispLSI

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

Logic

Array

D Q

GLB

1024EA

CLK

January 2002

0139/1024EA

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