IS42S16800D7TLI Integrated Silicon Solution, IS42S16800D7TLI Datasheet

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IS42S16800D7TLI

Manufacturer Part Number
IS42S16800D7TLI
Description
TSOP54
Manufacturer
Integrated Silicon Solution
Datasheet

Specifications of IS42S16800D7TLI

Date_code
08+
IS42S81600D
IS42S16800D
16Meg x 8, 8Meg x16
128-MBIT SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Industrial Temperature Availability
• Lead-free Availability
Integrated Silicon Solution, Inc. — www.issi.com
07/28/08
Rev. E
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
positive clock edge
IS42S81600D
IS42S16800D
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
V
3.3V 3.3V
3.3V 3.3V
DD
V
DDQ
KEY TIMING PARAMETERS
OVERVIEW
ISSI
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600D
4M x8x4 Banks
54-pin TSOPII
Parameter
Clk Cycle Time
Clk Frequency
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
's 128Mb Synchronous DRAM achieves high-speed
IS42S16800D
2M x16x4 Banks
54-pin TSOPII
54-ball BGA
166
125
5.4
6.5
-6
6
8
JULY 2008
143
100
5.4
6.5
10
-7
7
-75E
133
7.5
6.5
Unit
Mhz
Mhz
ns
ns
ns
ns
1

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