IS42S16400F6TL Integrated Silicon Solution, IS42S16400F6TL Datasheet

IS42S16400F6TL

Manufacturer Part Number

IS42S16400F6TL

Description

TSOP54

Manufacturer

Integrated Silicon Solution

Datasheet

1.IS42S16400F6TL.pdf (59 pages)

Specifications of IS42S16400F6TL

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IS42S16400F

IS45S16400F

FEATURES

• Clock frequency: 200, 166, 143, 133 MHz

• Fully synchronous; all signals referenced to a

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length

• Programmable burst sequence:

• Self refresh modes

• Auto refresh (CBR)

• 4096 refresh cycles every 64 ms (Com, Ind, A1

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

• Burst termination by burst stop and precharge

OPTIONS

• Package:

• Operating Temperature Range

Integrated Silicon Solution, Inc. — www.issi.com

Rev. I

12/01/2011

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

positive clock edge

– (1, 2, 4, 8, full page)

Sequential/Interleave

grade) or 16ms (A2 grade)

operations capability

command

54-pin TSOP II

54-ball FBGA (8mm x 8mm)

Commercial (0

Industrial (-40

Automotive Grade A1 (-40

Automotive Grade A2 (-40

C to +85

C to +70

C to +85

C to +105

KEY TIMING PARAMETERS

ADDRESS TABLE

OVERVIEW

ISSI

bits x 16-bit x 4-bank for improved performance. The

synchronous DRAMs achieve high-speed data transfer

using pipeline architecture. All inputs and outputs signals

refer to the rising edge of the clock input.

Parameter

Configuration

Refresh Count

Row Addresses

Column Addresses

Bank Address Pins

Auto Precharge Pins

Parameter

Clk Cycle Time

CAS Latency = 3

CAS Latency = 2

Clk Frequency

CAS Latency = 3

CAS Latency = 2

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

's 64Mb Synchronous DRAM is organized as 1,048,576

Com./Ind.

4M x 16

1M x 16 x 4

banks

4K/64ms

4K/16ms

A0-A11

A0-A7

BA0, BA1

A10/AP

DECEMBER 2011

200

133

7.5

-5

166

133

7.5

5.4

-6

143

133

7.5

5.4

-7

Unit

Mhz

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