IS42S16400D7BLI Integrated Silicon Solution, IS42S16400D7BLI Datasheet

IS42S16400D7BLI

Manufacturer Part Number

IS42S16400D7BLI

Description

TSOP54

Manufacturer

Integrated Silicon Solution

Datasheet

1.IS42S16400D7BLI.pdf (57 pages)

Specifications of IS42S16400D7BLI

Date_code

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IS42S16400D

FEATURES

• Clock frequency: 166, 143 MHz

• Fully synchronous; all signals referenced to a

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length

• Programmable burst sequence:

• Self refresh modes

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

• Burst termination by burst stop and precharge

• Byte controlled by LDQM and UDQM

• Industrial temperature availability

• Package: 400-mil 54-pin TSOP II, 60-ball fBGA

• Lead-free package is available

PIN DESCRIPTIONS

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. C

07/05/06

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

A0-A11

BA0, BA1

DQ0 to DQ15

CLK

CKE

RAS

CAS

positive clock edge

– (1, 2, 4, 8, full page)

Sequential/Interleave

operations capability

command

Address Input

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

Bank Select Address

Data I/O

1-800-379-4774

OVERVIEW

ISSI

as 1,048,576 bits x 16-bit x 4-bank for improved performance.

The synchronous DRAMs achieve high-speed data transfer

using pipeline architecture. All inputs and outputs signals

refer to the rising edge of the clock input.

PIN CONFIGURATIONS

54-Pin TSOP (Type II)

LDQM

UDQM

GND

's 64Mb Synchronous DRAM IS42S16400D is organized

GNDQ

VDDQ

LDQM

VDD

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VDD

CAS

RAS

VDD

BA0

BA1

A10

Write Enable

Lower Bye, Input/Output Mask

Upper Bye, Input/Output Mask

Power

Ground

Power Supply for DQ Pin

Ground for DQ Pin

No Connection

ISSI

JULY 2006

GND

DQ15

GNDQ

DQ14

DQ13

VDDQ

DQ12

DQ11

GNDQ

DQ10

DQ9

VDDQ

DQ8

GND

UDQM

CLK

CKE

A11

GND

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