IS42S16320B7TLI Integrated Silicon Solution, IS42S16320B7TLI Datasheet

IS42S16320B7TLI

Manufacturer Part Number

IS42S16320B7TLI

Description

TSOP54

Manufacturer

Integrated Silicon Solution

Datasheet

1.IS42S16320B7TLI.pdf (62 pages)

Specifications of IS42S16320B7TLI

Date_code

09+

Current page: 1 of 62
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IS42S86400B

IS42S16320B, IS45S16320B

64M x 8, 32M x 16

512Mb SYNCHRONOUS DRAM

FEATURES

• Clock frequency: 166, 143, 133 MHz

• Fully synchronous; all signals referenced to a

• Internal bank for hiding row access/precharge

• Power supply

IS42S86400B

• LVTTL interface

• Programmable burst length

• Programmable burst sequence:

• Auto Refresh (CBR)

• Self Refresh

• 8K refresh cycles every 16ms (A2 grade) or

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

• Burst termination by burst stop and precharge

• Available in 54-pin TSOP-II and 54-ball W-BGA

• Operating Temperature Range:

Integrated Silicon Solution, Inc. — www.issi.com

Rev. G

04/08/2011

out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain

the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-

plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

positive clock edge

IS42/45S16320B 3.3V 3.3V

– (1, 2, 4, 8, full page)

Sequential/Interleave

64 ms (Commercial, Industrial, A1 grade)

operations capability

command

(x16 only)

Commercial: 0

Industrial: -40

Automotive, A1: -40

Automotive, A2: -40

C to +85

C to +70

3.3V 3.3V

C to +85

C to +105

ddq

KEY TIMING PARAMETERS

OVERVIEW

ISSI

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

The 512Mb SDRAM is organized as follows.

IS42S86400B

16Mx8x4 Banks

54-pin TSOPII

Parameter

Clk Cycle Time

CAS Latency = 3

CAS Latency = 2

Clk Frequency

CAS Latency = 3

CAS Latency = 2

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

's 512Mb Synchronous DRAM achieves high-speed

IS42/45S16320B

8M x16x4 Banks

54-pin TSOPII

54-ball W-BGA

166

100

5.4

-6

APRIL 2011

143

100

5.4

-7

-75E Unit

133

7.5

5.5

–

Mhz

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