IS42S16100E6TLI Integrated Silicon Solution, IS42S16100E6TLI Datasheet

IS42S16100E6TLI

Manufacturer Part Number

IS42S16100E6TLI

Description

TSOP

Manufacturer

Integrated Silicon Solution

Datasheet

1.IS42S16100E6TLI.pdf (81 pages)

Specifications of IS42S16100E6TLI

Date_code

09+

Current page: 1 of 81
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IS42S16100E

IC42S16100E

FEATURES

• Clock frequency: 200, 166, 143 MHz

• Fully synchronous; all signals referenced to a

• Two banks can be operated simultaneously and

• Dual internal bank controlled by A11

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length

• Programmable burst sequence:

• 2048 refresh cycles every 32 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

• Burst termination by burst stop and

• Byte controlled by LDQM and UDQM

• Packages 400-mil 50-pin TSOP-II and 60-ball

• Lead-free package option

• Available in Industrial Temperature

PIN DESCRIPTIONS

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the

latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

01/22/08

512K Words x 16 Bits x 2 Banks (16-MBIT)

SYNCHRONOUS DYNAMIC RAM

A0-A11

A0-A10

A11

A0-A7

DQ0 to DQ15

CLK

CKE

RAS

positive clock edge

independently

(bank select)

– (1, 2, 4, 8, full page)

Sequential/Interleave

operations capability

precharge command

BGA

Address Input

Row Address Input

Bank Select Address

Column Address Input

Data DQ

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

DESCRIPTION

ISSI

IC42S16100E is organized as a 524,288-word x 16-bit

x 2-bank for improved performance. The synchronous

DRAMs achieve high-speed data transfer using pipeline

architecture. All inputs and outputs signals refer to the

rising edge of the clock input.

PIN CONFIGURATIONS

50-Pin TSOP (Type II)

CAS

LDQM

UDQM

VDD

GND

VDDQ

GNDQ

’s 16Mb Synchronous DRAM IS42S16100E/

GNDQ

VDDQ

LDQM

DQ7

VDD

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

CAS

RAS

A11

A10

Column Address Strobe Command

Write Enable

Lower Bye, Input/Output Mask

Upper Bye, Input/Output Mask

Power

Ground

Power Supply for DQ Pin

Ground for DQ Pin

No Connection

JANUARY 2008

GND

DQ15

IDQ14

GNDQ

DQ13

DQ12

VDDQ

DQ11

DQ10

GNDQ

DQ9

DQ8

VDDQ

UDQM

CLK

CKE

GND

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