IS41LV16105B50KLI Integrated Silicon Solution, IS41LV16105B50KLI Datasheet
IS41LV16105B50KLI
Manufacturer Part Number
IS41LV16105B50KLI
Description
TSOP
Manufacturer
Integrated Silicon Solution
Datasheet
1.IS41LV16105B50KLI.pdf
(20 pages)
Specifications of IS41LV16105B50KLI
Date_code
08+
IS41LV16105B
1M x 16 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
• Refresh Mode:
• JEDEC standard pinout
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range: -30
• Industrial Temperature Range: -40
• Lead-free available
PIN CONFIGURATIONS
44(50)-Pin TSOP (Type II)
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/18/05
VDD
VDD
VDD
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
NC
NC
NC
NC
NC
A0
A1
A2
A3
— 1,024 cycles/16 ms
— RAS-Only, CAS-before-RAS (CBR), and Hidden
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
42-Pin SOJ
VDD
VDD
RAS
VDD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
WE
NC
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
o
o
C to +85
C to +85
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
o
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
o
C
C
DESCRIPTION
The
mance CMOS Dynamic Random Access Memories. Fast Page
Mode allows 1,024 random accesses within a single row with
access cycle time as short as 20 ns per 16-bit word. The Byte
Write control, of upper and lower byte, makes the IS41LV16105B
ideal for use in 16-, 32-bit wide data bus systems.
These features make the IS41LV16105B ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The IS41LV16105B is packaged in a 42-pin 400-mil SOJ and
400-mil 44- (50-) pin TSOP (Type II).
KEY TIMING PARAMETERS
PIN DESCRIPTIONS
Parameter
Max. RAS Access Time (t
Max. CAS Access Time (t
Max. Column Address Access Time (t
Min. Fast Page Mode Cycle Time (t
Min. Read/Write Cycle Time (t
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
V
GND
NC
DD
ISSI
IS41LV16105B is 1,048,576 x 16-bit high-perfor-
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
Address Inputs
RAC
CAC
)
)
RC
)
PC
ISSI
)
AA
)
-50
50
13
25
20
84
APRIL 2005
104
-60
60
15
30
25
Unit
ns
ns
ns
ns
ns
®
1
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