74ALVCH16540DGG,51 NXP Semiconductors, 74ALVCH16540DGG,51 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16540DGG,51
• Description: IC INVERTER DUAL 8-INPUT 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16540DGG,51

• Logic Type: Inverter
• Number Of Inputs: 8
• Number Of Circuits: 2
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16540DG; 74ALVCH16540DG; 935210850512

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH16540 is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74ALVCH16540 is a 16-bit inverting buffer/line driver with
3-State outputs. The 3-State outputs are controlled by the output
enable inputs 1OE
to assume a high impedance OFF-state.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level. This feature eliminates the need for
external pull-up or pull-down resistors. The device can be used as
four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1997 Aug 11
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance multiple V
and ground bounce
Direct interface with TTL levels
Bus hold on all data inputs eliminates the need for external pull-up
resistors to hold unused inputs
Output drive capability 50 transmission lines @ 85 C
16-bit buffer/line driver, inverting,
5V input tolerant (3-State)
t
t
C
C
C
PHL
P
f
f
S (C
SYMBOL
i
o
I
PD
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
= C
/t
/t
L
PLH
is used to determine the dynamic power dissipation (P
PD
V
amb
PACKAGES
CC
TM
V
2
= 25 C; t
CC
flow-through standard pin-out architecture
Propagation delay
1An to 1Yn;
1An to 1Yn;
2An to 2Yn
Input capacitance
Power dissipation capacitance per buffer
Power dissipation capacitance per buffer
n
f
2
o
and 2OE
) = sum of outputs.
f
i
+ S (C
r
= t
CC
n
f
. A HIGH on nOE
L
and ground pins for minimum noise
2.5ns
L
PARAMETER
V
= output load capacitance in pF;
CC
CC
= supply voltage in V;
2
TEMPERATURE RANGE
f
o
) where:
–40 C to +85 C
–40 C to +85 C
n
causes the outputs
D
in mW):
C
V
C
V
V = GND to V
V
CC
CC
I
L
L
= GND to V
OUTSIDE NORTH AMERICA
= 50pF
= 30pF
= 3.3V
= 2.5V
2
74ALVCH16540 DGG
74ALVCH16540 DL
PIN CONFIGURATION
CC
CC
1
1
CONDITIONS
Outputs disabled
Outputs enabled
1OE
2OE
GND
GND
GND
GND
V
1Y4
1Y5
2Y3
V
2Y4
2Y6
2Y7
1Y0
1Y1
1Y2
1Y3
1Y6
1Y7
2Y0
2Y1
2Y2
2Y5
CC
CC
1
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
NORTH AMERICA
ACH16540 DGG
ACH16540 DL
SW00108
74ALVCH16540
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TYPICAL
1OE
1A0
1A1
GND
1A2
1A3
V
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
V
2A4
2A5
GND
2A6
2A7
2OE
Product specification
CC
CC
1.8
1.8
5.0
26
5
2
2
DWG NUMBER
853-2020 18266
SOT370-1
SOT362-1
UNIT
pF
pF
pF
ns
ns