EVAL-CONTROLBRD AD [Analog Devices], EVAL-CONTROLBRD Datasheet - Page 22

• Manufacturer Part Number: EVAL-CONTROLBRD
• Description: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/QFN
• Manufacturer: AD [Analog Devices]

AD7983
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7983s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7983s is shown
in Figure 36, and the corresponding timing is given in Figure 37.
ACQUISITION
CNV = SDI
SCK
SDO
SDO
SDO
t
A
B
C
HSCKCNV
= SDI
= SDI
A
B
C
CONVERSION
t
t
t
CONV
DSDOSDI
SSCKCNV
t
t
EN
DSDOSDI
SDI
t
HSDO
1
t
AD7983
SSDISCK
CNV
SCK
A
D
D
D
C
B
2
A
15
15
15
SDO
D
D
D
C
B
3
A
14
14
14
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
Figure 36. Chain Mode with Busy Indicator Connection Diagram
t
DSDO
D
D
D
t
SCKH
C
4
t
A
B
HSDISCK
13
13
13
SDI
AD7983
15
t
SCK
CNV
SCK
B
D
D
D
16
C
B
A
1
1
Rev. 0 | Page 22 of 24
1
SDO
t
SCKL
D
D
D
17
C
A
B
0
0
0
D
D
18
B
A
SDI
15
15
t
CYC
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest
to the digital host (see the AD7983 ADC labeled C in Figure 36)
is driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7983 then enters the acquisition phase and goes
into standby mode. The data bits stored in the internal shift
register are clocked out, MSB first, by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in the
chain outputs its data MSB first, and 16 × N + 1 clocks are required
to readback the N ADCs. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate and, consequently, more AD7983s in
the chain, provided the digital host has an acceptable hold time.
ACQUISITION
D
D
AD7983
19
B
A
14
14
t
ACQ
CNV
SCK
C
31
SDO
D
D
32
B
A
1
1
D
D
33
B
A
0
0
D
CONVERT
DATA IN
IRQ
CLK
34
A
DIGITAL HOST
15
D
35
A
14
47
D
t
48
DSDOSDI
A
1
t
DSDOSDI
t
DSDODSI
D
49
A
0