EVAL-ADMP441Z AD [Analog Devices], EVAL-ADMP441Z Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADMP441Z
• Description: Omnidirectional Microphone
• Manufacturer: AD [Analog Devices]

ADMP441
THEORY OF OPERATION
The
output, omnidirectional MEMS microphone with a bottom
port. The complete
sensor, signal conditioning, an analog-to-digital converter, anti-
aliasing filters, power management, and an industry standard
24-bit I2S interface.
The
Telephone Terminal Equipment Transmission Requirements for
Wideband Digital Wireline Telephones standard.
UNDERSTANDING SENSITIVITY
The casual user of digital microphones may have difficulty
understanding the sensitivity specification. Unlike an analog
microphone (whose specification is easily confirmed with an
oscilloscope), the digital microphone output has no obvious
unit of measure.
The
with an applied sound pressure level of 94 dB. The units are in
decibels referred to full scale. The
peak output word is 2
−26 dBFS of that scale is (2
acoustic tone at 1 kHz having a 1 Pa rms amplitude results in an
output digital signal whose peak amplitude is 420,426.
Although the industry uses a standard specification of 94 dB
SPL, the
The higher sound pressure level reduces noise and improves
repeatability. The
the sensitivity test result at 94 dB is derived with very high
confidence from the test data.
POWER MANAGEMENT
The
operation, standby mode, and power-down mode.
Normal Operation
The microphone becomes operational 2
with SCK at 3.072 MHz) after initial power-up. The CHIPEN
pin then controls the power modes. The part is in normal opera-
tion mode when SCK is active and the CHIPEN pin is high.
Standby Mode
The microphone enters standby mode when the serial data
clock SCK stops and CHIPEN is high. Normal operation
resumes 2
SCK restarts.
The
power-down mode, or vice versa. Standby mode is only
intended to be entered from the normal operation state.
ADMP441
ADMP441
ADMP441
ADMP441
ADMP441
ADMP441
14
clock cycles (5 ms with SCK at 3.072 MHz) after
is a high performance, low power, digital
complies with the TIA-920 Telecommunications
has a nominal sensitivity of −26 dBFS at 1 kHz
has three different power states: normal
should not be transitioned from standby to
ADMP441
ADMP441
test method applies a 104 dB SPL signal.
23
– 1 (integer representation), and
23
− 1) × 10
has excellent gain linearity, and
solution consists of a MEMS
ADMP441
(−26/20)
18
clock cycles (85 ms
= 420,426. A pure
default full-scale
Rev. A | Page 8 of 16
Power-Down Mode
The microphone enters power-down mode when CHIPEN is
low, regardless of the SCK operation. Normal mode operation
resumes 2
after CHIPEN returns high while SCK is active.
It always takes 2
is applied.
It is not recommended to supply active clocks (WS and SCK) to
the
this continuously turns on ESD protection diodes, which may
affect long-term reliability of the microphone.
STARTUP
The microphones have zero output for the first 2
cycles (85 ms with SCK at 3.072 MHz) following power-up.
I²S DATA INTERFACE
The slave serial data port’s format is I2S, 24-bit, twos comple-
ment. There must be 64 SCK cycles in each WS stereo frame, or
32 SCK cycles per data-word. The L/R control pin determines
whether the
For a stereo application, the SD pins of the left and right
ADMP441
Figure 9. The format of a stereo I2S data stream is shown in
Figure 10. Figure 11 and Figure 12 show the formats of a mono
microphone data stream for left and right microphones,
respectively.
Data Output Mode
The output data pin (SD) is tristated when it is not actively
driving I2S output data. SD immediately tristates after the LSB
is output so that another microphone can drive the common
data line.
The SD trace should have a pull-down resistor to discharge the
line during the time that all microphones on the bus have
tristated their outputs. A 100 kΩ resistor is sufficient for this, as
shown in Figure 9.
Data-Word Length
The output data-word length is 24 bits per channel. The
ADMP441
data-word (f
Data-Word Format
The default data format is I2S (twos complement), MSB-first. In
this format, the MSB of each word is delayed by one SCK cycle
from the start of each half-frame.
ADMP441
17
microphones should be tied together as shown in
must always have 64 clock cycles for every stereo
SCK clock cycles (43 ms with SCK at 3.072 MHz)
ADMP441
SCK
while there is no power supplied to V
= 64 × f
17
clock cycles to restart the
WS
outputs data in the left or right channel.
).
ADMP441
Data Sheet
18
SCK clock
DD
. Doing
after V
DD