EVAL-ADF4151EB1Z AD [Analog Devices], EVAL-ADF4151EB1Z Datasheet - Page 8

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EVAL-ADF4151EB1Z

Manufacturer Part Number
EVAL-ADF4151EB1Z
Description
Fractional-N/Integer-N PLL Synthesizer
Manufacturer
AD [Analog Devices]
Datasheet
Pin No.
22
25
26, 27
28
29
30
31
32
ADF4151
Mnemonic
R
LD
D
DV
REF
MUXOUT
SD
SDV
EP
SET
GND
GND
DD
IN
DD
Description
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the R
where:
R
I
Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of PLL
lock.
Digital Ground. Ground return path for DV
Digital Power Supply. This pin should be the same voltage as AV
should be placed as close as possible to this pin.
Reference Input. This is a CMOS input with a nominal threshold of V
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.
Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AV
to the ground plane are to be placed as close as possible to this pin.
The exposed pad must be connected to GND.
CP
SET
= 4.5 mA.
= 5.1 kΩ.
I
CP
=
SET
22.95
R
SET
pin is 0.49 V. The relationship between I
Rev. B | Page 8 of 28
DD
.
CP
and R
SET
DD
is
. Decoupling capacitors to the ground plane
DD
/2 and a dc equivalent input resistance
DD
x. Decoupling capacitors
Data Sheet

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