EVAL-AD7934-6CB AD [Analog Devices], EVAL-AD7934-6CB Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7934-6CB
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: AD [Analog Devices]

AD7934-6
Reading Data from the AD7934-6
With the W/ B pin tied logic high, the AD7934-6 interface
operates in word mode. In this case, a single read operation
from the device accesses the conversion data-word on Pins DB0
to DB11. The DB8/HBEN pin assumes its DB8 function. With
the W/ B pin tied to logic low, the AD7934-6 interface operates
in byte mode. In this case, the DB8/HBEN pin assumes its
HBEN function.
Conversion data from the AD7934-6 must be accessed in two
read operations with 8 bits of data provided on DB0 to DB7 for
each of the read operations. The HBEN pin determines whether
the read operation accesses the high byte or the low byte of the
12-bit word. For a low byte read, DB0 to DB7 provide the eight
LSBs of the 12-bit word. For a high byte read, DB0 to DB3
provide the 4 MSBs of the 12-bit word. DB4 and DB5 of the
high byte provide the channel ID. DB6 and DB7 are always 0.
Figure 34 shows the read cycle timing diagram for a 12-bit
transfer. When operated in word mode, the HBEN input does
not exist and only the first read operation is required to access
data from the device. When operated in byte mode, the two
read cycles shown in Figure 35 are required to access the full
data-word from the device.
DB0 TO DB7
HBEN/DB8
Figure 35. AD7934-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ B = 0)
CS
RD
t
t
13
15
t
10
LOW BYTE
t
12
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t
11
t
16
t
14
The CS and RD signals are gated internally and level triggered
active low. In either word mode or byte mode, CS and RD can
be tied together as the timing specification t
minimum. This means the bus is constantly driven by the
AD7934-6.
The data is placed onto the data bus a time, t
and RD go low. The RD rising edge can be used to latch data
out of the device. After a time, t
stated.
Alternatively, CS and RD can be tied permanently low, and the
conversion data is valid and placed onto the data bus a time, t
before the falling edge of BUSY.
Note that if RD is pulsed during the conversion time then this
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion by way of tying CS and
RD low does not cause any degradation.
t
17
t
15
HIGH BYTE
t
16
14
, the data lines become three-
10
13
and t
, after both CS
11
are 0 ns
9
,