EVAL-AD7843CB3 AD [Analog Devices], EVAL-AD7843CB3 Datasheet - Page 13

• Manufacturer Part Number: EVAL-AD7843CB3
• Description: Touch Screen Digitizer
• Manufacturer: AD [Analog Devices]

Detailed Serial Interface Timing
Figure 10 shows the detailed timing diagram for serial interfacing
to the AD7843. Writing of information to the Control Register
takes place on the first eight rising edges of DCLK in a data
transfer. The Control Register is only written to if a START bit
is detected (see Control Register section) on DIN and the initia-
tion of the following conversion is also dependent on the presence
of the START bit. Throughout the eight DCLK cycles when
data is being written to the part, the DOUT line will be driven
low. The MSB of the conversion result is clocked out on the
falling edge of the ninth DCLK cycle and is valid on the rising
edge of the tenth DCLK cycle, therefore nine leading zeros may
be clocked out prior to the MSB. This means the data seen on
the DOUT line in the twenty four DCLK conversion cycle, will
be presented in the form of nine leading zeros, twelve bits of
data and three trailing zeros.
The rising edge of CS will put the bus and the BUSY output
back into three-state, the DIN line will be ignored and if a con-
version is in progress at the time then this will also be aborted.
However, if CS is not brought high after the completion of the
X/Y SWITCHES (1,2)
(SER/DFR LOW)
X/Y SWITCHES (1)
(SER/DFR HIGH)
NOTES
1
2
Y DRIVERS ARE ON WHEN X
DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
WHEN PD1, PD0 = 10 OR 00, Y– WILL TURN ON AT END OF CONVERSION.
OR POWER-DOWN MODE IS CHANGED.
BUSY
DCLK
DIN
DOUT
CS
THREE-STATE
THREE-STATE
DCLK
BUSY
DOUT
(START)
DIN
CS
S
1
OFF
A2
IDLE
OFF
IS SELECTED INPUT CHANNEL (A2–A0 = 001), X DRIVERS ARE ON WHEN Y
A1
t
1
t
t
A0
2
3
MODE
t
7
SER/
DFR
t
t
8
4
AQUIRE
t
PD1 PD0
ON
ACQ
t
5
8
PD0
t
6
1
(MSB)
11
10
conversion cycle, then the part will wait for the next START bit
to initiate the next conversion. This means each conversion
need not necessarily be framed by CS, as once CS goes low the
part will detect each START bit and clock in the control word
after it on DIN. When the AD7843 is in the 12-bit conversion
mode, a second START bit will not be detected until seven DCLK
pulses have elapsed after a control word has been clocked in on
DIN, i.e., another START bit can be clocked in on the eighth
DCLK rising edge after a control word has been written to the
device (see Fifteen Clock Cycle section). If the device is in the
8-bit conversion mode, a second START bit will not be recog-
nized until three DCLK pulses have elapsed after the control
word has been clocked in, i.e., another START bit can be
clocked in on the fourth DCLK rising edge after a control word
has been written to the device.
Because a START bit can be recognized during a conversion, it
means the control word for the next conversion can be clocked
in during the current conversion, enabling the AD7843 to com-
plete a conversion cycle in less than twenty-four DCLKs.
ON
9
DB11
t
6
8
CONVERSION
7
t
DB10
9
OFF
6
5
8
IS SELECTED INPUT CHANNEL (A2–A0 = 101).
4
1
t
t
12
11
3
2
t
10
1
(LSB)
0
ZERO FILLED
AD7843
IDLE
OFF
THREE-STATE
THREE-STATE
8