LF2301 LODEV [LOGIC Devices Incorporated], LF2301 Datasheet - Page 2

• Manufacturer Part Number: LF2301
• Description: Image Resampling Sequencer
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
SIGNAL DEFINITIONS
Power
Vcc and GND
+5V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
P
P
Data input port. P
the rising edge of CLK.
B
B
Address input port. B
the rising edge of CLK.
Outputs
X
X
Address output port.
CA
CA
cient Address output port.
U
U
Address output port.
Controls
INIT — Initialize
When INIT is HIGH for a minimum of
two clock cycles, the control logic is
cleared and initialized for the start of a
new image transformation. When
INIT goes LOW, normal operation
begins after two clock cycles. INIT is
latched on the rising edge of CLK.
WEN — Write Enable
When
the device on P
preload register addressed by the data
11-0
11-0
3-0
3-0
11-0
11-0
11-0
11-0
7-0
7-0
— Parameter Register Address Input
is the 4-bit Parameter Register
— Parameter Register Data Input
is the 12-bit Parameter Register
— Source Address Output
— Target Address Output
is the 12-bit registered Source
is the 12-bit registered Target
— Coefficient Address Output
is the 8-bit registered Coeffi-
WEN is LOW,
11-0
11-0
is loaded into the
data latched into
3-0
is latched on
is latched on
latched into the device on B
WEN is HIGH, data cannot be loaded
into the preload registers and their
contents will not be changed. WEN is
latched on the rising edge of CLK.
LDR — Load Data Register
When LDR is HIGH, data in all
preload registers is latched into the
Transformation Parameter Registers.
When LDR is LOW, data cannot be
loaded into the Transformation
Parameter Registers and their contents
will not be changed. LDR is latched
on the rising edge of CLK.
ACC — Accumulate
The registered ACC output initializes
the accumulation register of the
external multiplier-accumulator. At
the start of each interpolation “walk,”
ACC goes LOW for one cycle effec-
tively clearing the storage register by
loading in only the new first product.
ACC from either the row or column
LF2301 may be used.
F
IGURE
WEN, NOOP, OETA
1. I
INIT, LDR,
P
CLK
B
MAGE
11-0
3-0
2-2
12
4
5
T
RANSFORMATION
3-0
. When
INTER
END
INTER
END
INTERPOLATION
COEFFICIENT
Image Resampling Sequencer
Generator
Generator
Address
Address
LF2301
LF2301
Column
CA
CA
RAM
Row
8
8
(X)
(Y)
7-0
7-0
S
UWRI — Target Memory Write Enable
The Target Memory Write Enable goes
LOW for one clock cycle after the end
of each interpolation “walk.” When
OETA is HIGH, this registered output
is forced to the high-impedance state.
UWRI from either the row or column
LF2301 may be used.
INTER — Interconnect
When two LF2301s are used to form
an ITS, the END flag on each device
is connected to INTER on the other
device. The END flag from the row
device indicates an “end of line” to the
column device. The END flag from the
column device indicates a “bottom of
frame” to the row device, forcing a
reset of the address counter.
NOOP — No Operation
When NOOP is LOW, the clock is
overridden holding all address
generators in their current state. X
and CA
YSTEM
UWRI
X
U
Y
V
ACC
11-0
11-0
11-0
11-0
Video Imaging Products
12
12
12
12
12
7-0
(ITS)
are forced to the high-
24
24
ACC
Y
X,Y,P
IMAGE DATA OUT
IMAGE DATA IN
LMA1009/2009
DESTINATION
Accumulator
12 x 12 bit
Multiplier-
SOURCE
IMAGE
IMAGE
08/16/2000–LDS.2301-H
12
RAM
12
D
12
RAM
12
OUT
X
LF2301
11-0