EVAL-AD7327CB AD [Analog Devices], EVAL-AD7327CB Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD7327CB
• Description: 500 kSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
V
T
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t
A
2
DD
= T
= 12 V to 16.5 V, V
MAX
to T
V
50
10
16 × t
75
12
25
45
26
57
0.4 × t
0.4 × t
13
40
10
4
2
750
500
25
MIN
DOUT
CC
SCLK
DIN
. Timing specifications apply with a 32 pF load, unless otherwise noted.
< 4.75 V
CS
THREE-
SCLK
STATE
SCLK
SCLK
SS
Limit at T
= −12 V to −16.5 V, V
WRITE
t
ADD2
2
1
3 IDENTIFICATION BITS
t
ADD1
3
V
50
10
16 × t
60
5
20
35
14
43
0.4 × t
0.4 × t
8
22
9
4
2
750
500
25
t
CC
SEL1
9
REG
MIN
= 4.75 V to 5.25 V
2
, T
SCLK
ADD0
SCLK
SCLK
MAX
SEL2
REG
3
SIGN
MSB
CC
= 2.7 V to 5.25 V, V
4
DB11
Figure 2. Serial Interface Timing Diagram
t
t
6
4
t
CONVERT
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
t
10
5
t
DB10
7
Rev. 0 | Page 7 of 36
Description
V
t
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal
reference
Power-up from full shutdown/autoshutdown mode, external
reference
DRIVE
SCLK
DRIVE
13
2
at 20 ns, the mark space ratio needs to be limited to 50:50.
= 1/f
DB2
= 2.7 V to 5.25 V, V
≤ V
SCLK
CC
14
t
5
DB1
LSB
15
DB0
1
DON’T
CARE
16
REF
THREE-STATE
= 2.5 V to 3.0 V internal/external,
t
8
DRIVE
t
QUIET
) and timed from a voltage level of 1.6 V.
t
1
AD7327