EVAL-AD1833AEB AD [Analog Devices], EVAL-AD1833AEB Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD1833AEB
• Description: 24-Bit, 192 kHz, DAC
• Manufacturer: AD [Analog Devices]

AD1833A
Pin No.
1
2
3, 4, 33, 34, 44
5, 6, 7, 30, 31, 32, 41
8, 29
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
35
36
37
38
39
Mnemonic IN/OUT
OUTLP1
OUTLN1
AV
AGND
DGND
DV
ZEROA
ZERO3R
ZERO3L
ZERO2R
CLATCH
CDATA
CCLK
L/RCLK
BCLK
MCLK
SDIN1
SDIN2
SDIN3
SOUT
ZERO2L
ZERO1R
ZERO1L
RESET
DV
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
DD
DD1
DD2
O
O
O
O
O
O
I
I
I
I/O
I
I
I/O
I/O
O
O
O
O
I
O
O
O
O
O
I/O
ZERO3R
OUTLP1
OUTLN1
ZERO3L
ZEROA
DV
AGND
AGND
AGND
DGND
AV
AV
DD1
DD
DD
PIN FUNCTION DESCRIPTIONS
10
11
12
1
2
3
4
5
6
7
8
9
Description
DAC 1 Left Channel Positive Output.
DAC 1 Left Channel Negative Output.
Analog Supply.
Analog Ground.
Digital Ground.
Digital Supply to Core Logic.
Flag to Indicate Zero Input on All Channels.
Flag to Indicate Zero Input on Channel 3 Right.
Flag to Indicate Zero Input on Channel 3 Left.
Flag to Indicate Zero Input on Channel 2 Right.
Latch Input for Control Data (SPI Port).
Serial Control Data Input (SPI Port).
Clock Input for Control Data (SPI Port).
Left/Right Clock for DAC Data Input; FSTDM Input in TDM Slave Mode;
FSTDM Output in TDM Master Mode.
Bit Clock for DAC Data Input; BCLKTDM Input in TDM Slave Mode; BCLKTDM
Output in TDM Master Mode.
Master Clock Input.
Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes).
Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC in
TDM Mode).
Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode).
Auxiliary I
Flag to Indicate Zero Input on Channel 2 Left.
Flag to Indicate Zero Input on Channel 1 Right.
Flag to Indicate Zero Input on Channel 1 Left.
Power-Down and Reset Control.
Power Supply to Output Interface Logic.
DAC 1 Right Channel Negative Output.
DAC 1 Right Channel Positive Output.
DAC 2 Right Channel Negative Output.
DAC 2 Right Channel Positive Output.
DAC 3 Right Channel Negative Output.
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN CONFIGURATION
PIN 1
IDENTIFIER
(Not to Scale)
2
AD1833A
TOP VIEW
S Output (Available in TDM Mode).
43 42 41 40
–6–
39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
OUTRP1
OUTRN1
AV
AV
AGND
AGND
AGND
DGND
DV
RESET
ZERO1L
ZERO1R
DD
DD
DD2
REV. 0