SP791CN SIPEX [Sipex Corporation], SP791CN Datasheet - Page 9

• Manufacturer Part Number: SP791CN
• Description: Low Power Microprocessor Supervisory with Battery Switch-Over
• Manufacturer: SIPEX [Sipex Corporation]

SP791DS/08
Figure 4. Adding an external pull-down resistor ensures
RESET is valid with V
MR low for a minimum of 25 s resets all the
internal counters, sets the Watchdog Output
(WDO) and Watchdog-Pulse Output (WDPO)
high, and sets the Set Watchdog-Timeout (SWT)
input to V
V
the Chip-Enable Output (CE
a high state. The RESET output remains at a
logic low as long as MR is held low, and the
reset-timeout period begins after MR returns
high, Figure 2.
Use this input as either a digital-logic input or a
second low-line comparator. Normal TTL/
CMOS levels can be wire-OR connected via
pull-down diodes, Figure 3, and open-drain/col-
lector outputs can be wire-ORed directly.
RESET OUTPUT
The SP791's RESET output ensures that the P
powers up in a known state, and prevents code-
execution errors during power-down or brown-
out conditions.
The RESET output is active low, and typically
sinks 3.2mA at 0.1V saturation voltage in its
active state. When deasserted, RESET sources
Figure 6. Two consecutive watchdog faults latch the system in reset.
OUT
(for Internal timeouts). It also, disables
OUT
Corporation
RESET
if it is not already connected to
REACTIVATE
CC
SP791 Low Power Microprocessor Supervisory with Battery Switch-Over
15
down to GND.
+5V
+5V
*
10k
1 F
OUT
TO P RESET
3.6V
) forcing it to
4.7k
9
1
V
MR
BATT
LOWLINE
GND
Vcc
4
Corporation
RESET
WDPO
3
WDO
V
WDI
OUT
16
14
9
15
11
10
2
SETS Q HIGH ON POWER-UP
Figure 5. WDI, WDO and WDPO Timing
Diagram (V
1.6mA at V
tery is used, RESET output is valid down to V
= 1V, and an external 10k pull-down resistor
on RESET ensures that RESET will be valid
with V
As V
RESET output switch reduces accordingly,
increasing the r
age. The 10k
parallel combination of switch and external
resistor is 10k and the output saturation volt-
age is below 0.4V, while sinking 40 A. When
using a 10k
high state for the RESET output with Vcc =
4.75V is 4.5V typical. For battery voltages
greater than or equal to 2V, RESET remains
valid for V
be asserted during the following conditions:
1) V
2) MR < 1.25V (typ)
3) RESET = logic "0" ; for 200 ms (typ) after
Vcc rises above 4.65V or after MR has exceeded
1.25V.
The SP791 battery-switchover comparator does
not affect RESET assertion.
1/6 74HC04
5
D
CLOCK
0.1 F
SET
WDPO
6
3
CC
WDO
WDI
CC
RESET Vss
CD4013
CC
Vcc
< 4.65V (typ)
14
4
goes below 1V, the gate drive to the
CC
down to GND as shown on Figure 4.
CC
7
Q
Q
OUT
mode).
1
2
between 0V and 5.5V. RESET will
external pull-down resistor, the
DS
pull-down resistor ensures the
– 0.5V. When no backup bat-
(ON) and the saturation volt-
70ns
1.6sec
RESET
INTERRUPT
I/O
NMI
© Copyright 2000 Sipex Corporation
P POWER
P
CONSECUTIVE
INDICATIONS
WATCHDOG
TWO
FAULT
100ns MIN
CC