AM29DL640G65 AMD [Advanced Micro Devices], AM29DL640G65 Datasheet - Page 9

• Manufacturer Part Number: AM29DL640G65
• Description: 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. Addresses are A21:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
3. If WP#/ACC = V
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ15–DQ0 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
June 7, 2002
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
Sector Unprotect (Note 2)
Temporary Sector
Unprotect
IN
= Address In, D
Block Protection and Unprotection” section.
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection
and Unprotection”. If WP#/ACC = V
Operation
IN
IL
, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V
= Data In, D
IL
V
0.3 V
CE#
, H = Logic High = V
CC
X
X
L
L
L
L
L
OUT
Table 1. Am29DL640G Device Bus Operations
OE#
H
X
H
X
H
H
X
L
= Data Out
HH
, all sectors will be unprotected.
WE# RESET#
H
H
X
X
X
L
L
L
P R E L I M I N A R Y
IH
V
, V
0.3 V
V
V
V
CC
H
H
H
L
ID
ID
ID
ID
IH
), A21:A-1 in byte mode (BYTE# = V
= 11.5–12.5 V, V
Am29DL640G
WP#/ACC
(Note 3)
(Note 3)
(Note 3)
L/H
L/H
L/H
L/H
L/H
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
HH
A1 = H, A0 = L
A1 = H, A0 = L
SA, A6 = H,
Addresses
SA, A6 = L,
= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
(Note 2)
A
A
A
X
X
X
IN
IN
IN
IH
, protection on sectors 0, 1, 140, and 141
BYTE#
High-Z
High-Z
High-Z
IH
= V
D
D
D
IL
OUT
X
X
. The BYTE# pin determines
).
IN
IN
IH
DQ15–DQ8
High-Z, DQ15 = A-1
DQ8–DQ14 =
BYTE#
IL
High-Z
High-Z
High-Z
High-Z
= V
. CE# is the power
X
X
IL
High-Z
High-Z
High-Z
DQ7–
D
DQ0
D
D
D
D
OUT
IN
IN
IN
IN
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