AM29DL640G65 AMD [Advanced Micro Devices], AM29DL640G65 Datasheet
AM29DL640G65
Related parts for AM29DL640G65
AM29DL640G65 Summary of contents
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PRELIMINARY Am29DL640G 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another ...
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GENERAL DESCRIPTION The Am29DL640G megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Option Standard Voltage Range: V Max Access Time (ns), t ACC CE# Access (ns OE# Access (ns BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL ...
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CONNECTION DIAGRAMS A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 9 A20 10 WE# 11 RESET# 12 A21 13 WP#/ACC 14 RY/BY# 15 A18 16 A17 ...
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CONNECTION DIAGRAMS A8 B8 RFU RFU A7 B7 A13 A12 WE# RESET RY/BY# WP#/ACC A17 RFU RFU Special Handling Instructions for BGA Packages ...
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PIN DESCRIPTION A21– Addresses DQ14–DQ0 = 15 Data Inputs/Outputs (x16-only de- vices) DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC ...
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... WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations Valid Combinations for BGA Packages Order Number EI Am29DL640G65 EI, EE Am29DL640G70 Am29DL640G90 Am29DL640G120 Am29DL640G F BGA), Package Marking PCI ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to ...
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Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control ...
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Table 2. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA23 0010000xxx SA24 0010001xxx SA25 0010010xxx SA26 0010011xxx SA27 0010100xxx SA28 0010101xxx SA29 0010110xxx SA30 0010111xxx SA31 0011000xxx SA32 0011001xxx SA33 0011010xxx SA34 0011011xxx SA35 0011000xxx SA36 0011101xxx SA37 ...
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Table 2. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA71 1000000xxx SA72 1000001xxx SA73 1000010xxx SA74 1000011xxx SA75 1000100xxx SA76 1000101xxx SA77 1000110xxx SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx SA82 1001011xxx SA83 1001100xxx SA84 1001101xxx SA85 ...
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Table 2. Am29DL640G Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 1110101xxx SA125 1110110xxx SA126 1110111xxx SA127 1111000xxx SA128 1111001xxx SA129 1111010xxx Bank 4 SA130 1111011xxx SA131 1111100xxx SA132 ...
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To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method Table 5. Am29DL640G Autoselect Codes, (High Voltage Method) A21 Description CE# OE# WE# A12 Manufacturer ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ...
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The alternate method intended only for programming equipment requires V on address pin A9 and OE#. ID This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. The device is shipped with all sectors unprotected. ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a ...
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The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until V is greater than V CC system must provide the proper signals to the ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 11. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 12 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper ...
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The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 12 shows the address and data requirements for ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 12 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase ...
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DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for infor- mation on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- ...
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Table 12. Am29DL640G Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) 6 Byte AAA SecSi Sector Factory Word ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 13 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +150 C Ambient Temperature with Power Applied . . . . . . . . ...
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DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current (Notes ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std. Description t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle bit t ASO polling t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t WC Valid PA Addresses t AH CE# OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 20. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Group Protect/Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect For sector unprotect ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following ...
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PHYSICAL DIMENSIONS FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA package June 7, 2002 Am29DL640G Dwg rev AF; 10/99 49 ...
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PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array ( BGA package Am29DL640G June 7, 2002 ...
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PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP June 7, 2002 Am29DL640G Dwg rev AA; 10/99 51 ...
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REVISION SUMMARY Revision A (November 7, 2001) Initial release. Revision A+1 (April 15, 2002) Global Changed data sheet status from Advance Information to Preliminary. Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and ...