AM29DL640D120EE AMD [Advanced Micro Devices], AM29DL640D120EE Datasheet - Page 21

• Manufacturer Part Number: AM29DL640D120EE
• Description: 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
and power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
system must provide the proper signals to the control
pins to prevent unintentional writes when V
greater than V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
December 13, 2005
Figure 3. Secured Silicon Sector Protect Verify
CC
CC
Write 40h to SecSi
Write Inhibit
Read from SecSi
Sector address
A1 = 1, A0 = 0
A1 = 1, A0 = 0
is less than V
Sector address
with A6 = 0,
Write 60h to
with A6 = 0,
any address
RESET# =
Wait 1 ms
V
LKO
IH
START
or V
.
ID
LKO
CC
, the device does not ac-
is greater than V
Remove V
If data = 00h,
SecSi Sector is
If data = 01h,
SecSi Sector is
from RESET#
Protect Verify
unprotected.
SecSi Sector
Write reset
protected.
command
complete
Table 12
IH
or V
CC
ID
power-up
for com-
LKO
. The
CC
Am29DL640D
CC
is
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The
system can read CFI information at the addresses
given in Tables 8–11. To terminate reading CFI data,
the system must write the reset command. The CFI
Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase
algorithm.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 8–11. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
IL
, CE# = V
IH
or WE# = V
IL
and OE# = V
IH
. To initiate a write cycle,
IH
during power up,
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