BS62LV4006ECG70 BSI [Brilliance Semiconductor], BS62LV4006ECG70 Datasheet - Page 7

• Manufacturer Part Number: BS62LV4006ECG70
• Description: Very Low Power CMOS SRAM 512K X 8 bit
• Manufacturer: BSI [Brilliance Semiconductor]

R0201-BS62LV4006
WRITE CYCLE 2
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All
3. t
4. During this period, DQ pins are in the output state so that the input signals of opposite
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
6. OE is continuously low (OE = V
7. D
8. D
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals
10. Transition is measured ± 500mV from steady state with C
11. t
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
phase to the outputs must not be applied.
transition, output remain in a high impedance state.
of opposite phase to the outputs must not be applied to them.
The parameter is guaranteed but not 100% tested.
WR
CW
OUT
OUT
is measured from the earlier of CE or WE going high at the end of write cycle.
is measured from the later of CE going low to the end of write.
is the same phase of write data of this write cycle.
is the read data of next address.
ADDRESS
CE
WE
D
D
OUT
IN
(1,6)
IL
).
t
AS
L
= 5pF.
(5)
t
WHZ
7
(4,10)
t
AW
t
t
CW
t
WP
WC
(11)
(2)
t
DW
t
t
OW
DH
BS62LV4006
(8,9)
(7)
Revision
Oct.
(8)
2008
1.5