K7R321882 Samsung semiconductor, K7R321882 Datasheet - Page 5

• Manufacturer Part Number: K7R321882
• Description: 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
• Manufacturer: Samsung semiconductor

K7R323682M
K7R321882M
K7R320982M
PIN CONFIGURATIONS
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 2A for 72Mb.
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
SYMBOL
G
M
CQ, C Q
A
B
C
D
E
F
H
K
L
N
P
R
J
Q0-8
V
D0-8
V
TMS
TDO
K, K
C, C
TCK
Doff
V
V
2. When ZQ pin is directly connected to V
B W
TDI
SA
ZQ
NC
W
DDQ
3. Not connected to chip pad internally.
R
REF
2. BW controls write to D0:D8 .
DD
SS
TDO
Doff
C Q
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,11D
1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
V
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
SS
V
TCK
NC
NC
NC
NC
NC
NC
Q6
NC
NC
D4
D5
D7
REF
2
/SA*
11M,11J,10E,11C,2D,2G,3L,2N,10P
11L,10J,11E,11B,3E,3G,2L,3P,11P
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
V
(TOP VIEW) K7R320982M(4Mx9)
SA
NC
NC
NC
Q4
NC
Q5
NC
NC
NC
NC
Q7
SA
D6
DDQ
3
R E F
10N,11N,1P,2P,9P
voltage.
PIN NUMBERS
D D
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
11A, 1A
2H,10H
6P, 6R
6B, 6A
V
V
V
V
V
V
V
V
V
V
V
SA
SA
SA
11H
10R
11R
W
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
1H
4A
8A
7B
2R
1R
4
SS
SS
SS
SS
1Mx36 & 2Mx18 & 4Mx9 QDR
V
V
V
V
V
V
V
V
V
NC
NC
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
- 5 -
V
V
V
V
V
V
V
V
V
SA
SA
C
C
6
K
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
7
SS
SS
DD
DD
DD
DD
DD
SS
SS
Nybble Write Control Pin,active when low
Output Driver Impedance Control Input
Output Power Supply ( 1.5V or 1.8V )
Read Control Pin,active when low
Write Control Pin,active when low
Input Clock for Output Data
V
V
V
V
V
V
V
Input Reference Voltage
V
V
V
V
JTAG Test Mode Select
JTAG Test Data Output
SA
SA
SA
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DLL Disable when low
Power Supply ( 1.8 V )
R
JTAG Test Data Input
8
SS
SS
SS
SS
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
Data Outputs
No Connect
Input Clock
Data Inputs
Ground
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
S A
S A
DDQ
9
TM
II b2 SRAM
V
TMS
NC
NC
NC
NC
NC
NC
NC
NC
NC
SA
D2
Q 1
D8
10
REF
Dec. 2003
Rev 2.0
TDI
NOTE
C Q
NC
NC
NC
Z Q
NC
NC
Q 3
D3
Q 2
D1
Q 0
D0
Q 8
11
1
2
3