NDS335 Fairchild, NDS335 Datasheet

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NDS335

Manufacturer Part Number
NDS335
Description
N-Channel Logic Level Enhancement Mode Field Effect Transistor
Manufacturer
Fairchild
Datasheet

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Absolute Maximum Ratings
Symbol
V
V
I
P
T
THERMAL CHARACTERISTICS
R
R
© 1997 Fairchild Semiconductor Corporation
________________________________________________________________________________
D
J
DSS
GSS
D
NDS335N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline
surface mount package.
,T
JA
JC
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
Maximum Power Dissipation
Operating and Storage Temperature Range
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
- Pulsed
T
A
= 25°C unless otherwise noted
(Note 1b)
(Note 1a)
(Note 1a)
(Note 1)
Features
1.7 A, 20 V. R
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOT
and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
capability.
R
DS(ON)
DS(ON)
NDS335N
-55 to 150
G
= 0.14
0.46
250
= 0.11
1.7
0.5
20
10
75
8
D
TM
@ V
-3 design for superior thermal
@ V
GS
GS
= 2.7 V
S
= 4.5 V.
DS(ON)
July 1996
.
NDS335 Rev.C
Units
°C/W
°C/W
°C
W
V
V
A

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NDS335 Summary of contents

Page 1

... High density cell design for extremely low R Exceptional on-resistance and maximum DC current capability 25°C unless otherwise noted A (Note 1a) - Pulsed (Note 1a) (Note 1b) (Note 1) July 1996 = 0. 2.7 V DS(ON 0. 4.5 V. DS(ON design for superior thermal . DS(ON NDS335N Units 20 8 1.7 10 0.5 0.46 -55 to 150 250 °C/W 75 °C/W NDS335 Rev °C ...

Page 2

... MHz 4 Gen 1 4 Min Typ Max Units µA 10 µA 100 nA -100 nA 0.5 0 0.3 0.5 0.8 0.084 0.14 0.13 0.25 0.065 0. 240 pF 130 6 0 NDS335 Rev.C ...

Page 3

... C/W when mounted on a 0.001 in pad of 2oz copper Scale letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. Conditions 0.42 A (Note Min Typ Max Units 0. 0.8 1 guaranteed by JC NDS335 Rev.C ...

Page 4

... Drain Current and Temperature 1.3 25°C 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 2.5 3 -50 -25 . Figure 6. Gate Threshold Variation 2.5 2.7 3.0 3.5 4 DRAIN CURRENT ( 125°C J 25°C -55° DRAIN CURRENT ( 250µ 100 125 T , JUNCTION TEMPERATURE (°C) J with Temperature. 5 150 NDS335 Rev.C ...

Page 5

... Figure 12. Switching Waveforms T = 125°C J 25°C -55°C 0.2 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD with Source Current and Temperature . 10V 15V GATE CHARGE (nC off d(off INVERTED PULSE WIDTH . NDS335 Rev.C 8 ...

Page 6

... V , DRAIN-SOURCE VOLTAGE (V) DS 4.5"x5" FR-4 Board Still Air V = 2.7V GS 0.1 0.2 0.3 2 2oz COPPER MOUNTING PAD AREA ( ( See Note 1b JA P(pk ( Duty Cycle response will 20 30 0.4 . 100 300 NDS335 Rev.C ...

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