UPD62MC NEC, UPD62MC Datasheet - Page 9

• Manufacturer Part Number: UPD62MC
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
• Manufacturer: NEC

2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 10 Bits
contents are automatically incremented in accordance with the instruction length (byte count) each time an
instruction is executed.
destination address written in the operand.
entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to
the PC.
2.2 Stack Pointer (SP): 1 Bit
when the return instruction (RET) is executed.
signal is generated and the PC becoming “000H”.
by means of a program.
2.3 Address Stack Register (ASR (RF)): 10 Bits
the ASR value even after the RET is executed.
Refers to the binary counter that holds the address information of the program memory.
The program counter contains the address of the instruction that should be executed next. Normally, the counter
However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
When reset, the value of the program counter becomes “000H”.
Refers to the 1-bit register which holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented
When reset, the stack pointer contents are cleared to “0”.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up thus a system reset
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The low-order 8 bits are arranged in the RF of the data memory as a dual-function RAM. The register holds
When reset, it holds the previous data (undefined when turning on the power).
Caution If the RF is accessed as the data memory, the high-order 2 bits of the ASR become undefined.
ASR
PC
ASR9
PC9
ASR8
Figure 2-2. Address Stack Register Organization
PC8
Figure 2-1. Program Counter Organization
ASR7
PC7
Data Sheet U14208EJ1V0DS00
ASR6
PC6
ASR5
PC5
PC4
ASR4
RF
PC3
ASR3
PC2
ASR2
PC1
ASR1
PC0
ASR0
PD62
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