UCN5810F Allegro, UCN5810F Datasheet - Page 4

• Manufacturer Part Number: UCN5810F
• Description: BiMOS II 10-BIT SERIAL-INPUT / LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
• Manufacturer: Allegro

A. Minimum Data Active Time Before Clock Pulse
B. Minimum Data Active Time After Clock Pulse
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial
Data
Input Input I
H
L
X
L = Low Logic Level
5810-F
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
BLANKING
(Data Set-Up Time) .......................................................................... 75 ns
(Data Hold Time) ............................................................................. 75 ns
Output Transistion ......................................................................... 500 ns
STROBE
(T
DATA IN
Clock
CLOCK
A
OUT
= +25°C,V
N
H
L
R
X
P
1
1
1
Shift Register Contents
I
R
R
R
X
P
2
2
1
1
2
H = High Logic Level
A
DD
C
I
R
R
R
X
P
3
3
2
2
3
B
= 5 V, Logic Levels are V
...
...
...
...
...
...
D
E
I
R
R
R
X
P
N-1
N-1
N-2
N-2
N-1
F
I
R
R
R
X
P
G
N
N
N-1
N-1
N
X = Irrelevant
Output
Serial
Data
R
R
R
X
P
N
N-1
N-1
N
DD
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Strobe
Input
P = Present State
and Ground)
H
L
Dwg. No. A-12,649A
I
R
P
X
1
1
1
Latch Contents
I
R
P
X
2
2
2
I
R
P
X
3
R = Previous State
3
3
...
...
...
...
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
I
R
P
X
N-1
N-1
N-1
Serial Data present at the input is transferred
Information present at any register is trans-
When the BLANKING input is high, the
R
P
I
X
N
N
N
Blanklng
H
L
I
P
L
1
1
I
P
L
Output Contents
2
2
I
P
L
3
3
... I
... P
... L
N-1
N-1
I
P
L
N
N