CDP1805 Intersil Corporation, CDP1805 Datasheet - Page 17

• Manufacturer Part Number: CDP1805
• Description: CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
• Manufacturer: Intersil Corporation

Instruction Set
The CDP1805AC and CDP1806AC instruction summary is
given in Table 1. Hexadecimal notation is used to refer to the
4-bit binary codes.
In all registers, bits are numbered from the least significant
bit (LSB) to the most significant bit (MSB) starting with 0.
MEMORY REFERENCE
LOAD IMMEDIATE
REGISTER LOAD IMMEDIATE
LOAD VIA N
LOAD ADVANCE
LOAD VIA X
LOAD VIA X AND ADVANCE
REGISTER LOAD VIA X AND
ADVANCE
STORE VIA N
STORE VIA X AND DECREMENT
REGISTER STORE VIA X AND
DECREMENT
REGISTER OPERATIONS
INCREMENT REG N
DECREMENT REG N
DECREMENT REG N AND LONG
BRANCH IF NOT EQUAL 0
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HIGH REG N
REGISTER N TO REGISTER X
COPY
LOGIC OPERATIONS (Note 19)
OR
OR IMMEDIATE
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
AND
R(W): Register designated by W, where
W = N or X, or P
INSTRUCTION
MACHINE
CYCLES
NO. OF
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES)
2
5
2
2
2
2
5
2
2
5
2
2
5
2
2
2
2
2
4
2
2
2
2
2
CDP1805AC, CDP1806AC
MNEMONIC
STXD
RSXD
DBNZ
LDXA
RLXA
RLDI
DEC
GLO
RNX
XOR
AND
LDN
LDA
LDX
STR
PLO
GHI
ORI
INC
PHI
XRI
LDI
IRX
OR
17
OP CODE
Operation Notation
This notation means: The memory byte pointed to by R(N) is
loaded into D, and R(N) is incremented by 1.
(Note 10)
(Note 10)
(Note 10)
(Note 10)
68CN
68AN
682N
68BN
686N
AN
BN
0N
4N
5N
1N
2N
8N
9N
FB
F8
F0
72
73
60
F1
F9
F3
F2
R(W).0: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
M (R(N))
M(R(N))
R(N) + 1
M(R(X)) XOR D
M(R(P)) XOR D
M(R(P))
M(R(P))
R(N).0; R(P) + 2
M(R(N))
M(R(X))
M(R(X))
M(R(X))
R(N).0; R(X)) + 2
D
D
R(N).0
M(R)(X) - 1); R(X) - 2
R(N) - 1
R(N) - 1
M(R(P))
R(P).0, ELSE R(P) + 2
R(X) + 1
R(N).0
D
R(N).1
D
R(N)
M(R(X)) OR D
M(R(P)) OR D
R(P) + 1
M(R(X)) AND D
M(RN))
M(R(X)); R(X) - 1
R(N).0
R(N).1
D; R(N) + 1
R(X)
M(R(X)); R(N).1
D
D
D; R(P) + 1
R(N).1; M(R(P)) + 1
D; FOR N NOT 0
D; R(N) + 1
D
D; R(X) + 1
R(N).1; M(R(X) + 1)
R(N)
R(N); IF R(N) NOT 0,
R(P).1, M(R(P) + 1)
R(X)
R(P)
R(N)
D
D; R(P) + 1
D
D;
D
R(P)
OPERATION
R(X)
R(N)
R (X)
R(X)
R(P)
R(P)
R(X)
R(N)
R(P)