SAA5531 Philips Semiconductors, SAA5531 Datasheet - Page 43

• Manufacturer Part Number: SAA5531
• Description: Enhanced TV microcontrollers with On-Screen Display OSD
• Manufacturer: Philips Semiconductors

Philips Semiconductors
17.4
Page clearing is performed on request from either the Data
Capture block, or the microcontroller under the control of
the embedded software.
At power-on and reset the whole of the page memory is
cleared. The TXT13.PAGE CLEARING bit will be set while
this takes place.
17.4.1
When a page header is acquired for the first time after a
new page request or a page header is acquired with the
erase (C4) bit set the page memory is ‘cleared’ to spaces
before the rest of the page arrives.
When this occurs, the space code (20H) is written into
every location of rows 1 to 23 of the basic page memory,
the appropriate packet 27 row of the extension packet
memory and the row where teletext packet 24 is written.
This last row is either row 24 of the basic page memory, if
the TXT0.X24 POSN bit is set, or row 0 of the extension
packet memory, if the bit is not set. Page clearing takes
place before the end of the TV line in which the header
arrived which initiated the page clear.
This means that the 1 field gap between the page header
and the rest of the page which is necessary for many
teletext decoders is not required.
17.4.2
The software can also initiate a page clear, by setting the
TXT9.CLEAR MEMORY bit. When it does so, every
location in the memory block pointed to by
TXT15.BLOCK<3:0> is cleared to a space code (20H).
The CLEAR MEMORY bit is not latched so the software
does not have to reset it after it has been set.
Only one page can be cleared in a TV line so if the
software requests a page clear it will be carried out on the
next TV line on which the Data Capture hardware does not
force the page to be cleared. A flag, TXT13.PAGE
CLEARING, is provided to indicate that a software
requested page clear is being carried out. The flag is set
when a logic 1 is written into the TXT9.CLEAR MEMORY
bit and is reset when the page clear has been completed.
If TXT0.INV ON bit = 1 and a page clear is initiated on
Block 8 all locations are cleared to 00H.
2000 Feb 23
Enhanced TV microcontrollers with
On-Screen Display (OSD)
Page clearing
D
S
OFTWARE PAGE CLEAR
ATA
C
APTURE PAGE CLEAR
43
18 DATA CAPTURE
The Data Capture section takes in the analog Composite
Video and Blanking Signal (CVBS), and from this extracts
the required data, which is then decoded and stored in
memory.
The extraction of the data is performed in the digital
domain. The first stage is to convert the analog CVBS
signal into a digital form. This is done using an ADC
sampling at 12 MHz. The data and clock recovery is then
performed by a Multi-rate Video Input Processor (MulVIP).
From the recovered data and clock the following data
types are extracted WST Teletext (625/525), Closed
Caption, VPS and WSS. The extracted data is stored in
either memory (DRAM) via the Memory interface or in SFR
locations.
18.1
Two CVBS inputs
Video Signal Quality detector
Data Capture for 625-line WST
Data Capture for 525-line WST
Data Capture for US Closed Caption
Data Capture for VPS data (PDC system A)
Data Capture for Wide Screen Signalling (WSS) bit
decoding
Automatic selection between 525 WST/625 WST
Automatic selection between 625 WST/VPS on
line 16 of Vertical Blanking Interval
Real-time capture and decoding for WST Teletext in
hardware, to enable optimized microprocessor
throughput
Up to 10 pages stored on-chip
Inventory of transmitted Teletext pages stored in the
Transmitted Page Table (TPT) and Subtitle Page Table
(SPT)
Automatic detection of FASTEXT transmission
Real-time packet 26 engine in hardware for processing
accented, G2 and G3 characters
Signal quality detector for WST/VPS data types
Comprehensive Teletext language coverage
Full Field and Vertical Blanking Interval (VBI) data
capture of WST data.
Data Capture features
Preliminary specification
SAA55xx