GS82032 ETC, GS82032 Datasheet - Page 19
![no-image](/images/no-image-200.jpg)
GS82032
Manufacturer Part Number
GS82032
Description
64K x 32 2M Synchronous Burst SRAM
Manufacturer
ETC
Datasheet
1.GS82032.pdf
(23 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
GS82032AGT-5
Manufacturer:
NATIONAL
Quantity:
527
Company:
Part Number:
GS82032AT-4
Manufacturer:
CATALYS
Quantity:
244
Company:
Part Number:
GS82032AT-5
Manufacturer:
PHILIPS
Quantity:
978
Part Number:
GS82032AT-5
Manufacturer:
GSI
Quantity:
20 000
Company:
Part Number:
GS82032Q-5
Manufacturer:
MURATA
Quantity:
4 342
Part Number:
GS82032Q-5
Manufacturer:
GSI
Quantity:
20 000
Part Number:
GS82032T-133
Manufacturer:
GSI
Quantity:
20 000
Part Number:
GS82032T-4
Manufacturer:
GSI
Quantity:
20 000
Part Number:
GS82032T-5
Manufacturer:
VIA
Quantity:
20 000
GS82032AT/Q-180/166/133/100
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKH tKL
ADSP
ADSC
tZZH
tZZS
tZZR
ZZ
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.09 7/2002
19/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.