HYS64T128021GDL Infineon, HYS64T128021GDL Datasheet - Page 22
![no-image](/images/no-image-200.jpg)
HYS64T128021GDL
Manufacturer Part Number
HYS64T128021GDL
Description
200-Pin Small Outline Dual-In-Line Memory Module
Manufacturer
Infineon
Datasheet
1.HYS64T128021GDL.pdf
(48 pages)
4.1
For testing the IDD parameters, the timing parameters as in
Table 15
Parameter
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Active bank A to Active bank B command
delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
4.2
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A[6,2] in the EMRS(1) a
“weak” or “strong” termination can be selected. The
Table 16
Parameter
Enabled ODT current per DQ
ODT is HIGH; Data Bus inputs are FLOATING
Active ODT current per DQ
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
I
I
ODT (On Die Termination) Current
ODT current per terminated pin
DD
DD
Measurement Test Condition
Test Conditions
Symbol
CL
t
t
t
t
t
t
t
t
t
CKmin
RCDmin
RCmin
RRDmin
RASmin
RASmax
RPmin
RFCmin
REFI
min
HYS64T[32000/64020/128021][G/H]DL–[3.7/5]–A
Symbol
I
I
ODTO
ODTT
22
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
Table 15
Min. Typ. Max.
5
2.5
10
5
-3.7
PC2-4200-4-4-4 PC2-3200-3-3-3
4
3.75
15
60
10
45
70000
15
105
7.8
6
3
12
6
are used.
I
7.5
3.75
15
7.5
DD
Specifications and Conditions
512 Mbit DDR2 SDRAM
-5
3
5
15
55
10
40
70000
15
105
7.8
Unit
mA/DQ
mA/DQ
mA/DQ
mA/DQ
09122003-FTXN-KM26
Rev. 0.91, 2004-06
EMRS(1) State
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 0, A2 = 1
A6 = 1, A2 = 0
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
CK
s