GS832272 ETC, GS832272 Datasheet - Page 14

• Manufacturer Part Number: GS832272
• Description: (GS832218 / GS832236 / GS832272) S/DCD Sync Burst SRAMs
• Manufacturer: ETC

Synchronous Truth Table
Rev: 1.06 9/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
Deselect Cycle, Power Down
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Begin Burst
X = Don’t Care, H = High, L = Low
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Operation
Address Used
External
External
External
Current
Current
Current
Current
None
Next
Next
Next
Next
Diagram
14/41
State
Key
CW
CW
CR
CR
W
X
R
R
5
GS832218(B/E)/GS832236(B/E)/GS832272(C)
E
H
H
H
H
H
L
L
L
X
X
X
X
1
ADSP
H
H
H
H
H
H
X
L
X
X
X
X
ADSC
H
H
H
H
H
H
H
H
L
X
L
L
ADV
H
H
H
H
X
X
X
X
L
L
L
L
© 2001, GSI Technology
W
Preliminary
X
X
F
T
F
F
T
T
F
F
T
T
3
High-Z
DQ
Q
Q
D
Q
Q
D
D
Q
Q
D
D
4