HYS64T128020GU Infineon, HYS64T128020GU Datasheet - Page 25
![no-image](/images/no-image-200.jpg)
HYS64T128020GU
Manufacturer Part Number
HYS64T128020GU
Description
240-Pin Unbuffered DDR2 SDRAM Modules
Manufacturer
Infineon
Datasheet
1.HYS64T128020GU.pdf
(67 pages)
- Current page: 25 of 67
- Download datasheet (2Mb)
Table 16
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low.
max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
and address bus inputs are STABLE during DESELECTS.
1)
2) For details and notes see the relevant INFINEON component data sheet
Table 17
Product Type
Organization
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1) Calculated values from component data. ODT disabled.
Data Sheet
DD0
DD1
DD2P
DD2F
DD2Q
DD3P( MRS = 0)
DD3P( MRS = 1)
DD3N
DD4R
DD4W
DD5B
DD5D
DD6
DD7
V
DDQ
= 1.8 V ± 0.1 V;
I
I
DD
DD
Measurement Conditions
Specification
256MB
×64
1 Rank
–3.7
Max.
320
360
16
160
120
64
20
160
400
440
520
24
16
880
V
DD
= 1.8 V ± 0.1 V
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512MB
×64
1 Rank
–3.7
Max.
520
600
32
320
240
128
40
320
720
760
1040
48
32
1120
1)2)
t
RC
512MB
×72
1 Rank
–3.7
Max.
(cont’d)
I
585
675
36
360
270
144
45
360
810
855
1170
54
36
1260
without violating
DD6
current values are guaranteed up to
I
DD1
25
,
I
I
out
DD4R
1GB
×64
2 Ranks
–3.7
Max.
552
632
64
640
480
256
80
640
752
792
1072
96
64
1152
= 0 mA.
and
t
RRD
I
using a burst length of 4. Control
DD7
are defined with the outputs disabled
I
1GB
×72
2 Ranks
–3.7
Max.
621
711
72
720
540
288
90
720
846
891
1206
108
72
1296
DD
Specifications and Conditions
512 Mbit DDR2 SDRAM
T
CASE
09122003-GZEK-H4J6
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.87, 2004-06
of 85 °C
Notes
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
Symbol
I
I
DD6
DD7
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