MT8LSDT3264A Micron Technology, MT8LSDT3264A Datasheet - Page 7

• Manufacturer Part Number: MT8LSDT3264A
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron Technology

General Description
are high-speed CMOS, dynamic random-access,
256MB and 512MB memory modules organized in x64
configurations. These modules use internally config-
ured quad-bank SDRAMS with a synchronous inter-
face (all signals are registered on the positive edge of
the clock signals CK0-CK3).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank; A0–A12
select the device row). The address bits registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.
WRITE burst length of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An AUTO PRE-
CHARGE function may be enabled to provide a self-
timed row precharge that is initiateda the end of the
burst sequence.
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures,
but it also allows the column address to be changed on
every clock cycle to achieve a high-speed, fully random
access. Precharging one device bank while accessing
one of the other three device banks will hide the pre-
charge cycles and provide seamless, high-speed, ran-
dom-access operation.
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
syncronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between intenal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.
For more information regarding SDRAM operation,
refer to the 256Mb SDRAM component data sheet.
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
The MT8LSDT13264A(I) and MT16LSDT6464A(I)
Read and write accesses to the SDRAM modules are
The modules provide for programmable READ or
The modules use an internal pipelined architecture
The modules are designed to operate in 3.3V, low-
SDRAM modules offer substantial advances in
7
Serial Presence-Detect Operation
(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses.
SDRAM Functional Description
DRAMs that operate at 3.3V and include a synchro-
nous interface (all signals are registered on the positive
edge of the clock signal, CLK). The four banks of the x8
configured devices used for these modules are config-
ured as 8,192 bit-rows by 1,024 bit-columns, by 8
input/output bits.
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the active command are
used to select the device bank and row to be accessed;
BA0 and BA1 select the device bank, A0–A12 select the
device row. The address bits A0–A9 registered coinci-
dent with the READ or WRITE command are used to
select the starting device column location for the burst
access.
tialized. The following sections provide detailed infor-
mation
definition, command descriptions and device opera-
tion.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constrants specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
These modules incorporate serial presence-detect
In general, the 256Mb SDRAMs are quad-bank
Read and write accesses to the SDRAM are burst ori-
Prior to normal operation, the SDRAM must be ini-
SDRAMS must be powered up and initialized in a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
covering
168-PIN SDRAM DIMMs
256MB / 512MB (x64)
device
initialization,
DD
and V
©2002, Micron Technology Inc.
DDQ
(simulta-
register
2
C bus