MT8LSDT3264A Micron Technology, MT8LSDT3264A Datasheet - Page 17

• Manufacturer Part Number: MT8LSDT3264A
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: Micron Technology

Notes
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
10.
11. AC timing and I
12. Other input signals are allowed to transition no
13. I
14. Timing actually specified by
15. Timing actually specified by
8. In addition to meeting the transition rate specifi-
1. All voltages referenced to V
2. This parameter is sampled. V
3. IDD is dependent on output loading and cycle
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-up,
7. AC characteristics assume
9. Outputs measured at 1.5V with equivalent load:
T
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured (Com-
mercial Temperature: 0°C £ T
trial Temperature: -40°C £ T
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
must be powered up simultaneously. V
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
t
the open circuit condition; it is not a reference to
V
t
3V, with timing referenced to 1.5V crossover point.
If the input transition time is longer than 1ns,
then the timing is referenced at V
(MIN) and no longer at the 1.5V crossover point.
more than once every two clocks and are other-
wise at valid V
properly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle
rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
A
OH
IH
= 25°C; pin under test biased at 1.4; f = 1 MHz.
and V
specifications are tested after the device is
or V
OL
IL
. The last valid data element will meet
(or between V
IH
Q
or V
DD
tests have V
IL
levels.
t
IL
SS
T = 1ns.
A
t
.
and V
WR plus
t
50pF
£ +85 ° C).
CKS; clock(s) speci-
A
DD
+70°C and Indus-
IL
IL
, V
= 0V and V
IH
(MAX) and V
DDQ
) in a mono-
DD
t
RP; clock(s)
SS
and V
and V
= +3.3V;
DDQ
IH
SSQ
IH
=
17
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. The value of
30. For -10E, CL= 2 and
31. CKE is HIGH during refresh command period
32. Leakage number reflects the worst-case leakage
33. Leakage number reflects the worst-case leakage
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency
alteration for the test condition.
two clocks.
during this period.
133 and -13E.
width £ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
shoot: V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
budget (
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
t
and is guaranteed by design.
ule SPDs is calculated from
and
t
actually a nominal value and does not result in a
fail value.
possible through the module pin, not what each
memory device contributes.
possible through the module pin, not what each
memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns
RFC (MIN) else CKE is LOW. The I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
t
overshoot: V
WR, and PRECHARGE commands). CKE may
t
CK = 7.5ns; for -13E, CL = 2 and
DD
IL
current will increase or decrease propor-
t
RP) begins 7ns for -13E; 7.5ns for -133
t
168-PIN SDRAM DIMMs
CK = 10ns for -10E, and
(MIN) = -2V for a pulse width £ 3ns.
256MB / 512MB (x64)
t
RAS used in -13E speed grade mod-
IH
(MAX) = V
t
CK = 10ns; for -133, CL = 3
t
RC -
t
WR.
DDQ
t
RP = 45ns.
©2002, Micron Technology Inc.
t
+ 2V for a pulse
CK = 7.5ns for -
t
CK = 7.5ns.
DD
6 limit is
IL
under-