UPD23C32080AL NEC, UPD23C32080AL Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/4/470/nec_sml.jpg)
UPD23C32080AL
Manufacturer Part Number
UPD23C32080AL
Description
(UPD23C32040AL / UPD23C32080AL) 32M-BIT MASK-PROGRAMMABLE ROM
Manufacturer
NEC
Datasheet
1.UPD23C32080AL.pdf
(24 pages)
AC Characteristics (T
Note t
Remark
AC Test Conditions
10
Address access time
Page access time
Address skew time
Chip enable access time
Output enable access time
Output hold time
Output disable time
WORD, /BYTE access time
Input waveform (Rise
Output waveform
Output load
1) When switching /CE from high level to low level, t
2) When switching /CE from low level to high level, t
3) When /CE is fixed to low level, t
Since specs are defined for t
from high level to low level following address determination, or when the address is changed after /CE is switched
from low level to high level.
SKEW
1TTL + 100 pF
next address is determined.
/CE high level input point.
determined.
t
high impedance state output.
Parameter
DF
indicates the following three types of time depending on the condition.
is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
A
= –10 to +70 °C, V
/
Fall time ≤ ≤ ≤ ≤ 5 ns)
Symbol
t
t
t
SKEW
SKEW
t
t
t
t
t
ACC
PAC
OE
OH
WB
CE
DF
only when /CE is active, t
1.4 V
1.4 V
SKEW
Test condition
CC
is the time from the address change start point until the next address is
= 2.7 to 3.6 V)
Note
Data Sheet M15772EJ3V0DS
SKEW
SKEW
MIN.
Test points
Test points
0
0
V
CC
is the time from the /CE low level input point until the
is the time from the address change start point to the
= 3.0 V ± 0.3 V
SKEW
µ µ µ µ PD23C32040AL, 23C32080AL
TYP.
is not subject to limitations when /CE is switched
MAX.
100
100
100
25
10
25
25
1.4 V
1.4 V
MIN.
0
0
V
CC
= 3.3 V ± 0.3 V
TYP.
MAX.
90
25
10
90
25
25
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns