K4D263238E Samsung, K4D263238E Datasheet
K4D263238E
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K4D263238E Summary of contents
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... K4D263238E-GC 128Mbit GDDR SDRAM with Bi-directional Data Strobe and DLL Samsung Electronics reserves the right to change products or specification without notice 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM (144-Ball FBGA) Revision 1.7 November 2003 - 1 - 128M GDDR SDRAM Rev 1.7 (Nov. 2003) ...
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... Typo corrected Revision 1.4 (April 30, 2003) • Added Lead free package part number in the datasheet Revision 1.3 (April 14, 2003) • K4D263238E-GC2A/33/36 support wide voltage range from 2.375V to 2.94V Revision 1.2 (April 7, 2003) • Removed K4D263238E-GL36 from the spec. Revision 1.1 (March 17, 2003) • Typo corrected Revision 1.0 (February 13, 2003) • ...
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... GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications ...
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... K4D263238E-GC PIN CONFIGURATION DQS0 DM0 VSSQ C DQ4 VDDQ NC D DQ6 DQ5 VSSQ E DQ7 VDDQ VDD F DQ17 DQ16 VDDQ DQ19 DQ18 VDDQ G H DQS2 DM2 NC J DQ21 DQ20 VDDQ DQ22 DQ23 VDDQ K CAS WE VDD L RAS BA0 N NOTE: 1. RFU1 is reserved for A12 2 ...
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... K4D263238E-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input DQS ~ DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply ...
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... K4D263238E-GC BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D263238E-GC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D263238E-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D263238E-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. Output logic high voltage and low voltage is depend on output channel condition. 8. VDD/VDDQ = 2.8V ± 5% for K4D263238E-GC25 9. VDD/VDDQ = 2.5V ± 5% for K4D263238E-GC2A/33/36/40/ K4D263238E-GC2A/33/36 support wide voltage range from 2.375V to 2.94V. Symbol ...
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... K4D263238E-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current ...
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... K4D263238E-GC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Note case of differential clocks(CK and CK), input reference voltage for clock and CK ’s crossing point Accordingly, clock duty should be measured and CK ’ ...
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... K4D263238E-GC AC CHARACTERISTICS Parameter Symbol CL cycle time CL high level width low level width CL t DQS out access time from CK DQSCK t Output access time from Data strobe edge to Dout edge DQSQ t Read preamble RPRE t Read postamble RPST valid DQS-in ...
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... K4D263238E-GC Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
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... AC CHARACTERISTICS (II) K4D263238E-GC25 Frequency Cas Latency 400MHz ( 2.5ns ) 5 K4D263238E-GC2A Frequency Cas Latency 350MHz ( 2.86ns ) 4 300MHz ( 3.3ns ) 4 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 3 K4D263238E-GC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 3 -25 -2A -33 Min Max Min Max Min Max ...
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... K4D263238E-GC K4D263238E-GC36 Frequency Cas Latency 275MHz ( 3.6ns ) 4 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 3 K4D263238E-GC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 3 K4D263238E-GC45 Frequency Cas Latency 222MHz ( 4.5ns ) 3 Simplified Timing( CK, CK BA[1:0] BAa BAa Ra A8/AP Ra ADDR (A0~A7 A9,A10) WE DQS DQ Da0 Da1 Da2 Da3 ...
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... K4D263238E-GC PACKAGE DIMENSIONS (144-Ball FBGA) 0.45 0.35 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0.10 Max 0 ± 0. ± 0.05 Max <Bottom View> 128M GDDR SDRAM 12.0 A1 INDEX MARK 0.8 0.40 0.40 Rev 1.7 (Nov. 2003) Unit : mm ...