LRS1341 Sharp, LRS1341 Datasheet - Page 10
LRS1341
Manufacturer Part Number
LRS1341
Description
Stacked Chip 16M Flash Memory and 2M SRAM
Manufacturer
Sharp
Datasheet
1.LRS1341.pdf
(24 pages)
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LRS1341/LRS1342
Write Cycle (F-WE Controlled)
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as
2. Refer to the ‘Flash Memory Command Definition’ section for valid A
10
Write Cycle Time
F-RP HIGH Recovery to F-WE going to LOW
F-CE Setup to F-WE going LOW
F-WE Pulse Width
F-RP V
F-WP V
F-V
Address Setup to F-WE going HIGH
Data Setup to F-WE going HIGH
Data Hold from F-WE HIGH
Address Hold from F-WE HIGH
F-CE Hold from F-WE HIGH
F-WE Pulse Width HIGH
F-WE HIGH to F-RY/BY going LOW
Write Recovery before Read
F-V
F-RP V
F-WP V
T
during read-only operations. Refer to AC Characteristics for Read Cycle.
A
PP
PP
= -25°C to +85°C, V
Setup to F-WE going HIGH
Hold from Valid SRD, F-RY/BY HIGH-Z
HH
HH
IH
IH
Setup to F-WE going HIGH
Hold from Valid SRD, F-RY/BY HIGH
Setup to F-WE going HIGH
Hold from Valid SRD, F-RY/BY HIGH-Z
PARAMETER
CC
= 2.7 V to 3.6 V
2
2
1
SYMBOL
t
t
t
PHHWH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
WLWH
SHWH
DVWH
WHDX
WHEH
WHWL
PHWL
VPWH
AVWH
WHAX
WHRL
WHGL
ELWL
QVPH
AVAV
QVVL
QVSL
and D
IN
for block erase or word write.
MIN.
100
100
100
100
10
50
50
50
30
0
0
0
0
0
0
0
0
Stacked Chip (16M Flash & 2M SRAM)
MAX.
100
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet