AM79C989JCT Advanced Micro Devices, AM79C989JCT Datasheet - Page 27

• Manufacturer Part Number: AM79C989JCT
• Description: Quad Ethernet Switching Transceiver (QuEST)
• Manufacturer: Advanced Micro Devices

Status Register (Reg 19)
The Status Register (Reg 19) contains Read/Only (R/
O) and Cleared on Read (COR) bits which indicate
Error Mask Register (Reg 20)
The Error Mask Register (Reg 20) determines which
errors will be reported in the Summary Register (Reg
16). The Error Mask Register contains Read/Write
Bit(s)
Bit(s)
15:3
15:3
2
1
0
2
1
0
Receive Polarity
Receive Polarity
Rate Mismatch
Reversed Error
Rate Mismatch
Error Enabled
Jabber Error
Jabber Error
Reserved
Reserved
Reversed
Enable
Enable
Name
Name
Error
Written and read as zero.
1 = Frames received underflowed or overflowed the elasticity FIFO;
0 = No rate mismatch has occurred.
Register bit is cleared on Read.
1 = Receive polarity of the 10BASE-T receivers is reversed;
0 = Receive polarity is correct.
1 = 10BASE-T transmit circuit is in the Jabber state;
0 = 10BASE-T transmit circuit not in the Jabber state.
This bit is automatically cleared when the jabber condition
terminates.
Written and read as zero.
1 = Rate Mismatch Error reportable in the Summary Register;
0 = Rate Mismatch Error not reportable in the Summary Register.
1 = Receive Polarity Reversed reportable in the Summary Register
as an Error;
0 = Receive Polarity Reversed bit not reportable as an error in the
Summary Register.
1 = Jabber error reportable in the Summary Register;
0 = Jabber error not reportable in the Summary Register.
Table 19. Error Mask Register (Reg 20)
P R E L I M I N A R Y
Am79C989
Description
Description
status beyond the Auto-Negotiation status registers.
This register is duplicated for each port.
(R/W) or Read/Only (R/O) bits. If an error does occur
and the Mask enable bit is set the Error bit in the Sum-
mary Register (Reg 17) will not be asserted. This reg-
ister is duplicated for each port.
R/O, COR
Read/
Read/
Write
Write
R/W
R/W
R/W
R/O
R/O
R/O
R/O
Default/
Default/
Reset
Reset
0
0
0
0
0
0
0
0
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