AM79C989JCT Advanced Micro Devices, AM79C989JCT Datasheet - Page 21

• Manufacturer Part Number: AM79C989JCT
• Description: Quad Ethernet Switching Transceiver (QuEST)
• Manufacturer: Advanced Micro Devices

Device ID Registers (Reg 2-3)
Device ID Registers (Reg 2-3) contain Read/Only
(R/O) bits. Registers 2 and 3 designate a unique De-
vice ID: the manufacturer ID is designated by Reg 2 bits
Auto-Negotiation Advertisement Register (Reg 4)
The Auto-Negotiation Advertisement Register (Reg 4)
contains Read/Write (R/W) or Read/Only (R/O) bits.
This register contains the advertised ability of the
QuEST device. This register is duplicated on a per port
Note: When this register is modified, Restart Auto-Negotiation (Reg 0, bit 9) must be set to advertise the change.
Bit(s)
Bit(s)
15:10
Bit(s)
12:11
15:0
10:7
9:4
3:0
4:0
15
14
13
6
5
PHY_ID[31:16]
PHY_ID[15:10]
Selector Field
PHY_ID[9:4]
PHY_ID[3:0]
Remote Fault
Full Duplex
Half duplex
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Reserved
Reserved
Reserved
Name
Name
Name
Table 11. Auto-Negotiation Advertisement Register (Reg 4)
Bits 3-18 of the IEEE Organizationally
Unique Identifier.
Bits 19-24 of the IEEE Organizationally
Unique Identifier.
QuEST Model Number
Revision Number
1 = Next page exchange requested;
0 = Next page exchange not requested.
Written and read as zero.
1 = Remote fault bit is inserted into the base link code word during
the Auto-Negotiation process;
0 = The base link code work will have the bit position for remote fault
as cleared.
Written and read as zero.
Written and read as zero.
1 = Full Duplex capability is advertised;
0 = Full Duplex capability is not advertised.
1 = Half Duplex capability is advertised;
0 = Half Duplex capability is not advertised
The QuEST device is an IEEE 802.3 compliant device.
Description
Description
P R E L I M I N A R Y
Table 10. Register 3
Table 9. Register 2
Am79C989
Description
15:0 and Reg 3 bits 15:10; the model number is desig-
nated by Reg 3 bits 9:4; the Revision Number is desig-
nated by Reg 3 bits 3:0. This register is not duplicated
for each port.
basis. The purpose of this register is to advertise the
technology ability to the link partner device. When this
register is modified, Restart Auto-Negotiation (Reg 0,
bit 9) must be set to advertise the change.
Read/Write
Read/Write
R/O
R/O
R/O
R/O
Default/Reset
Default/Reset
0000 0000
0000 0000
(binary)
(binary)
1010
1111
0000
01
01
Read/
Write
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/O
Default/Reset
Default/Reset
(Hex)
(Hex)
0000
1A
1F
Default/
0
Reset
0x01
0
0
0
1
0
0
0
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