AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 70

• Manufacturer Part Number: AM79C978
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: Advanced Micro Devices

Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS
(CSR15, bit 3). If DXMTFCS is cleared to 0, the trans-
mitter will generate and append the FCS to the trans-
mitted frame. If the automatic padding feature is
invoked (APAD_XMT is set in CSR4), the FCS will be
appended by theAm79C978 controller regardless of
the state of DXMTFCS or ADD_FCS (TMD1, bit 29).
Note that the calculated FCS is transmitted most signif-
icant bit first. The default value of DXMTFCS is 0 after
H_RESET.
ADD_FCS (TMD1, bit 29) allows the automatic gener-
ation and transmission of FCS on a frame-by-frame
basis. DXMTFCS should be cleared to 0 in this mode.
To generate FCS for a frame, ADD_FCS must be set in
all descriptors of a frame (STP is set to 1). Note that bit
29 of TMD1 has the function of ADD_FCS if SWSTYLE
(BCR20, bits 7-0) is programmed to 0, 2, or 3.
Transmit Exception Conditions
Exception conditions for frame transmission fall into
two distinct categories: those conditions which are the
result of normal network operation, and those which
occur due to abnormal network and/or host related
events.
Normal events which may occur and which are handled
autonomously by theAm79C978 controller include col-
lisions within the slot time with automatic retry.
TheAm79C978 controller will ensure that collisions
which occur within 512 bit times from the start of trans-
mission (including preamble) will be automatically re-
tried with no host intervention. The transmit FIFO
ensures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of preamble plus address, length, and data
fields have been transmitted onto the network without
encountering a collision. Note that if DRTY (CSR15, bit
5) is set to 1 or if the network interface is operating in
full-duplex mode, no collision handling is required, and
any byte of frame data in the FIFO can be overwritten
as soon as it is transmitted.
If 16 total attempts (initial attempt plus 15 retries) fail,
theAm79C978 controller sets the RTRY bit in the cur-
rent transmit TDTE in host memory (TMD2), gives up
ownership (resets the OWN bit to 0) for this frame, and
processes the next frame in the transmit ring for trans-
mission.
Abnormal network conditions include:
n Loss of carrier
n Late collision
n SQE Test Error (does not apply to 100 Mbps net-
70
works.)
Am79C978
These conditions should not occur on a correctly con-
figured IEEE 802.3 network operating in half-duplex
mode. If they do, they will be reported. None of these
conditions will occur on a network operating in full-
duplex mode. (See the section Full-Duplex Operation
for more detail.)
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be cleared until the STP (the next
frame) is found.
Loss of Carrier
LCAR will be reported for every frame transmitted if
theAm79C978 controller detects a loss of carrier.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). TheAm79C978 controller will abandon the
transmit process for that frame, set Late Collision
(LCOL) in the associated TMD2, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be retried. Recovery from this condi-
tion must be performed by upper layer software.
SQE Test Error
If the network port is in Link Fail state, CERR will be
asserted in the 10BASE-T mode after transmit. CERR
will never cause INTA to be activated. It will, however,
set the ERR bit CSR0.
Receive Operation
The receive operation and features of theAm79C978
controller are controlled by programmable options.
TheAm79C978 controller offers a large receive FIFO to
provide frame buffering for increased system latency,
automatic flushing of collision fragments (runt packets),
automatic receive pad stripping, and a variety of ad-
dress match options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the IEEE 802.3 frame
format.
All receive frames can be accepted by setting the
PROM bit in CSR15. Acceptance of unicast and broad-
cast frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Ad-
dress register (CSR12 to CSR14) stores the address
that theAm79C978 controller compares to the destina-
tion address of the incoming frame for a unicast ad-
dress match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast
address match.